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AD7643 Fiches technique(PDF) 11 Page - Analog Devices

No de pièce AD7643
Description  18-Bit, 1.25 MSPS PulSAR ADC
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

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AD7643
Rev. 0 | Page 10 of 28
Pin
No.
Mnemonic
Type1
Description
31
RD
DI
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
32
CS
DI
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled.
CS is also used to gate the external clock in slave serial mode.
33
RESET
DI
Reset Input. When high, resets the AD7643. Current conversion, if any, is aborted. Falling edge of
RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface
section. If not used, this pin can be tied to DGND.
34
PD
DI
Power-Down Input. When high, powers down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed.
35
CNVST
DI
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state
and initiates a conversion.
37
REF
AI/O
Reference Output/Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally
supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal
reference and buffer. Refer to the Voltage Reference Input section.
38
REFGND
AI
Reference Input Analog Ground.
39
IN−
AI
Differential Negative Analog Input.
40
NC
No Connect.
43
IN+
AI
Differential Positive Analog Input.
45
TEMP
AO
Temperature Sensor Analog Output. Normally, 278 mV @ 25°C with a temperature coefficient
of 1 mV/°C. This pin can be used to measure the temperature of the AD7643. See the
Temperature Sensor section.
46
REFBUFIN
AI/O
Internal Reference Output/Reference Buffer Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical)
band gap output on this pin, which needs external decoupling. The internal fixed gain reference
buffer uses this to produce 2.048 V on the REF pin.
When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high),
applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section.
47
PDREF
DI
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down and an external reference must been used.
48
PDBUF
DI
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered down.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
Table 7. Data Bus Interface Definition
MODE
MODE1
MODE0
D0/OB/2C
D1/A0
D2/A1
D[3]
D[4:9]
D[10:11]
D[12:15]
D[16:17]
Description
0
0
0
R[0]
R[1]
R[2]
R[3]
R[4:9]
R[10:11]
R[12:15]
R[16:17]
18-Bit Parallel
1
0
1
OB/2C
A0 = 0
R[2]
R[3]
R[4:9]
R[10:11]
R[12:15]
R[16:17]
16-Bit High Word
1
0
1
OB/2C
A0 = 1
R[0]
R[1]
All Zeros
16-Bit Low Word
2
1
0
OB/2C
A0 = 0
A1 = 0
All Hi-Z
R[10:11]
R[12:15]
R[16:17]
8-Bit High Byte
2
1
0
OB/2C
A0 = 0
A1 = 1
All Hi-Z
R[2:3]
R[4:7]
R[8:9]
8-Bit Mid Byte
2
1
0
OB/2C
A0 = 1
A1 = 0
All Hi-Z
R[0:1]
All Zeros
8-Bit Low Byte
2
1
0
OB/2C
A0 = 1
A1 = 1
All Hi-Z
All Zeros
R[0:1]
8-Bit Low Byte
3
1
1
OB/2C
All Hi-Z
Serial Interface
Serial Interface


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