AD7643 datasheet(7/29 Pages) AD

No de pièce	AD7643

Description	18-Bit, 1.25 MSPS PulSAR ADC

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AD7643

Rev. 0 | Page 6 of 28

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1]

0

1

DIVSCLK[0]

Symbol

0

1

0

1

Unit

SYNC to SCLK First Edge Delay Minimum

t18

1

3

ns

Internal SCLK Period Minimum

t19

8

16

32

64

ns

Internal SCLK Period Maximum

t19

20

40

70

135

ns

Internal SCLK High Minimum

t20

2

8

16

32

ns

Internal SCLK Low Minimum

t21

2

8

16

32

ns

SDOUT Valid Setup Time Minimum

t22

1

5

ns

SDOUT Valid Hold Time Minimum

t23

0

0.5

10

30

ns

SCLK Last Edge to SYNC Delay Minimum

t24

0

0.5

9

26

ns

BUSY High Width Maximum

t28

0.84

1.14

1.72

2.88

μs

NOTE

IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND

SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD

CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

500µA

IOL

500µA

IOH

1.4V

TO OUTPUT

CL

50pF

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SCLK Outputs, CL = 10 pF

0.8V

2V

0.8V

2V

tDELAY

Figure 3. Voltage Reference Levels for Timing

Numéro de pièce similaire - AD7643

Fabricant	No de pièce	Fiches technique	Description
Analog Devices	AD7643	818Kb / 32P	16-Bit, 750 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC REV. 0
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Description similaire - AD7643

Fabricant	No de pièce	Fiches technique	Description
Analog Devices	AD7643	683Kb / 28P	18-Bit, 1.25 MSPS PulSAR REV. 0
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	AD7625BCPZ	673Kb / 24P	16-Bit, 6 MSPS, PulSAR Differential ADC REV. A
	AD7986BCPZ	472Kb / 28P	18-Bit, 2 MSPS PulSAR 15 mW ADC in LFCSP (QFN) REV. B

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