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MT9V032 Fiches technique(PDF) 51 Page - ON Semiconductor |
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MT9V032 Fiches technique(HTML) 51 Page - ON Semiconductor |
51 / 61 page MT9V032 www.onsemi.com 51 Table 13. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Minimum Maximum Unit VSUPPLY Power supply voltage (all supplies) –0.3 4.5 V ISUPPLY Total power supply current – 200 mA IGND Total ground current – 200 mA VIN DC input voltage –0.3 VDD + 0.3 V VOUT DC output voltage –0.3 VDD + 0.3 V TSTG1 Storage temperature –40 +125 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 5. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability . Table 14. AC ELECTRICAL CHARACTERISTICS (VPWR = 3.3V ±0.3V; TA = Ambient = 25°C; Output Load = 10pF) Definition Symbol Condition Min Typ Max Unit SYSCLK Input clock frequency Note 1 13.0 26.6 27.0 MHz Clock duty cycle 45.0 50.0 55.0 % tR Input clock rise time 1 2 5 ns tF Input clock fall time 1 2 5 ns tPLHP SYSCLK to PIXCLK propagation delay CLOAD = 10pF 3 7 11 ns tPD PIXCLK to valid DOUT(9:0) propagation delay CLOAD = 10pF –2 0 2 ns tSD Data setup time 14 16 – ns tHD Data hold time 14 16 – ns tPFLR PIXCLK to LINE_VALID propagation delay CLOAD = 10pF –2 0 2 ns tPFLF PIXCLK to FRAME_VALID propagation delay CLOAD = 10pF –2 0 2 ns 6. The frequency range specified applies only to the parallel output mode of operation. Propagation Delays for PIXCLK and Data Out Signals The pixel clock is inverted and delayed relative to the master clock. The relative delay from the master clock (SYSCLK) rising edge to both the pixel clock (PIXCLK) falling edge and the data output transition is typically 7ns. Note that the falling edge of the pixel clock occurs at approximately the same time as the data output transitions. See Table 14 for data setup and hold times. Propagation Delays for FRAME_VALID and LINE_VALID Signals The LINE_VALID and FRAME_VALID signals change on the same rising master clock edge as the data output. The LINE_VALID goes HIGH on the same rising master clock edge as the output of the first valid pixel’s data and returns LOW on the same master clock rising edge as the end of the output of the last valid pixel’s data. As shown in the Output Data Timing, FRAME_VALID goes HIGH 143 pixel clocks before the first |
Numéro de pièce similaire - MT9V032_17 |
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Description similaire - MT9V032_17 |
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