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MT9P401 Fiches technique(PDF) 9 Page - ON Semiconductor |
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MT9P401 Fiches technique(HTML) 9 Page - ON Semiconductor |
9 / 45 page MT9P401 CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE www.onsemi.com 9 Figure 10. Frame Timing LV Column Readout t ROW W Blanking Region WDC Active Image Dark Rows Frame Time The pixel clock (PIXCLK) represents the time needed to sample 1 pixel from the array, and is typically equal to 1 EXTCLK period. The sensor outputs data at the maximum rate of 1 pixel per PIXCLK. One row time (tROW) is the period from the first pixel output in a row to the first pixel output in the next row. The row time and frame time are defined by equations in Table 8. Table 8. FRAME TIME Parameters Name Equation Default Timing at EXTCLK = 96 MHz fps Frame Rate 1/tFRAME 14 tFRAME Frame Time (H + max(VB, VBMIN)) × tROW 71.66 ms tROW Row Time 2 × tPIXCLK × max(((W/2) + max(HB, HBMIN)), (41 + 346 × (Row_Bin+1) + 99)) 36.38 μs tROW_Default Row Time 2 × tPIXCLK × max(((W/2) + max(HB, HBMIN)), (41 + 346 × (Row_Bin+1) + 99)) 36.38 μs tROW_HDTV Row Time 2 × tPIXCLK × max(((W/2) + max(HB, HBMIN)), (41 + 186 × (Row_Bin+1) + 99)) 24.4 μs W Output Image Width 2 × ceil((Column_Size + 1) / (2 × (Column_Skip + 1))) 2592 PIXCLK H Output Image Height 2 × ceil((Row_Size + 1) / (2 × (Row_Skip + 1))) 1944 rows SW Shutter Width max (1, (2 16 × Shutter_Width_Upper) + Shutter_Width_Lower) 1943 rows HB Horizontal Blanking Horizontal_Blank + 1 1 PIXCLK VB Vertical Blanking Vertical_Blank + 1 26 rows HBMIN Minimum Horizontal Blanking 346 × (Row_Bin + 1) + 64 + (WDC / 2) 450 PIXCLK VBMIN Minimum Vertical Blanking max (8, SW − H) + 1 9 rows tPIXCLK Pixclk Period 1/fPIXCLK 10.42 ns |
Numéro de pièce similaire - MT9P401_17 |
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Description similaire - MT9P401_17 |
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