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MT9M114 Fiches technique(PDF) 34 Page - ON Semiconductor

No de pièce MT9M114
Description  High?륞efinition (HD) System?륮n?륾?륝hip (SOC) Digital Image Sensor
Download  45 Pages
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MT9M114 Fiches technique(HTML) 34 Page - ON Semiconductor

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MT9M114
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34
HARDWARE FUNCTIONS
Two-Wire Serial Interface
The two-wire serial interface bus enables read and write
access to control and status registers and variables within the
MT9M114.
The interface protocol uses a master/slave model in which
a master controls one or more slave devices. The MT9M114
always operates in slave mode. The host (master) generates
a clock (SCLK) that is an input to the MT9M114 and is used
to synchronize transfers. Data is transferred between the
master and the slave on a bidirectional signal (SDATA).
The host should always ensure that the following
relationship is adhered to.
S
CLK v
PIXEL CLOCK
22
Protocol
Data transfers on the two-wire serial interface bus are
performed by a sequence of low-level protocol elements, as
follows:
1. a (repeated) start condition
2. a slave address/data direction byte
3. a 16-bit register address (8-bit addresses are not
supported)
4. an (a no) acknowledge bit
5. a 16-bit data transfer (8-bit data transfers are not
supported)
6. a stop condition
The bus is idle when both SCLK and SDATA are HIGH.
Control of the bus is initiated with a start condition, and the
bus is released with a stop condition. Only the master can
generate the start and stop conditions.
A start condition is defined as a HIGH-to-LOW transition
on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start
condition without previously generating a stop condition;
this is known as a repeated start or restart condition.
A stop condition is defined as a LOW-to-HIGH transition
on SDATA while SCLK is HIGH.
Data is transferred serially, 8 bits at a time, with the most
significant bit (MSB) transmitted first. Each byte of data is
followed by an acknowledge bit or a no-acknowledge bit.
This data transfer mechanism is used for the slave
address/data direction byte and for message bytes. One data
bit is transferred during each SCLK clock period. SDATA can
change when SCLK is LOW and must be stable while SCLK
is HIGH.
Slave Address
Bits [7:1] of this byte represent the device slave address
and bit [0] indicates the data transfer direction. A “0” in
bit [0] indicates a WRITE, and a “1” indicates a READ. If
the SADDR signal is driven LOW, then addresses used by the
MT9M114 are R0x090 (write address) and R0x091 (read
address). If the SADDR signal is driven HIGH, then
addresses used by the MT9M114 are R0x0BA (write
address) and R0x0BB (read address).
Message Byte
Message bytes are used for sending register addresses and
register write data to the slave device and for retrieving
register read data. The protocol used is outside the scope of
the two-wire serial interface specification.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit
or a no-acknowledge bit in the SCLK clock period following
the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The
receiver indicates an acknowledge bit by driving SDATA
LOW. As for data transfers, SDATA can change when SCLK
is LOW and must be stable while SCLK is HIGH.
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver
does not drive SDATA low during the SCLK clock period
following a data transfer. A no-acknowledge bit is used to
terminate a read sequence.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition
on SDATA while SCLK is HIGH.
Typical Serial Transfer
A typical read or write sequence begins by the master
generating a start condition on the bus. After the start
condition, the master sends the 8-bit slave address/data
direction byte. The last bit indicates whether the request is
for a read or a write, where a “0” indicates a write and a “1”
indicates a read. If the address matches the address of the
slave device, the slave device acknowledges receipt of the
address by generating an acknowledge bit on the bus.
If the request was a write, the master then transfers the
16-bit register address to which a write should take place.
This transfer takes place as two 8-bit sequences and the slave
sends an acknowledge bit after each sequence to indicate
that the byte has been received. The master then transfers the
data as an 8-bit sequence; the slave sends acknowledge bit
at the end of the sequence. After 8 bits have been transferred,
the slave’s internal register address is automatically
incremented, so that the next 8 bits are written to the next
register address. The master stops writing by generating
a (re)start or stop condition.
If the request was a read, the master sends the 8-bit write
slave address/data direction byte and 16-bit register address,
just as in the write request. The master then generates
a (re)start condition and the 8-bit read slave address/data
direction byte, and clocks out the register data, 8 bits at a
time. The master generates an acknowledge bit after each
8-bit transfer. The slave’s internal register address is
automatically incremented after every 8 bits are transferred.
The data transfer is stopped when the master sends
a no-acknowledge bit.


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