AD7634

Data Sheet

Rev. B | Page 10 of 32

Pin No.

Mnemonic

Type1

Description

22

D11 or

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus.

SDCLK

When MODE[1:0] = 3, Serial Data Clock. In all serial modes, this pin is used as the serial data clock input

or output, dependent on the logic state of the EXT/INT pin. The active edge where the data SDOUT is

updated depends on the logic state of the INVSCLK pin.

23

D12 or

DO

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus.

SYNC

When MODE[1:0] = 3, Serial Data Frame Synchronization. In serial master mode (MODE[1:0] = 3,

EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal

data clock.

When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the

SDOUT output is valid.

When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the

SDOUT output is valid.

24

D13 or

DO

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.

RDERROR

When MODE[1:0] = 3, Serial Data Read Error. In serial slave mode (MODE[1:0] = 3, EXT/INT = high), this

output is used as an incomplete data read error flag. If a data read is started and not completed when

the current conversion is completed, the current data is lost and RDERROR is pulsed high.

25

D14 or

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 14 of the parallel port data output bus.

HW/SW

When MODE[1:0] = 3, Serial Configuration Hardware/Software Select. In serial mode, this input is used

to configure the AD7634 by hardware or software. See the Hardware Configuration section and

Software Configuration section.

When HW/SW = low, the AD7634 is configured through software using the serial configuration register.

When HW/SW = high, the AD7634 is configured through dedicated hardware input pins.

26

D15 or

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 15 of the parallel port data output bus.

SCIN

When MODE[1:0] = 3, Serial Configuration Data Input. In serial software configuration mode (HW/SW =

low), this input is used to serially write in, MSB first, the configuration data into the serial configuration

register. The data on this input is latched with SCCLK. See the Software Configuration section.

27

D16 or

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 16 of the parallel port data output bus.

SCCLK

When MODE[1:0] = 3, Serial Configuration Clock. In serial software configuration mode (HW/SW = low),

this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated

depends on the logic state of the INVSCLK pin. See the Software Configuration section.

28

D17 or

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 17 of the parallel port data output bus.

SCCS

When MODE[1:0] = 3, Serial Configuration Chip Select. In serial software configuration mode

(HW/SW = low), this input enables the serial configuration port. See the Software Configuration section.

29

BUSY

DO

Busy Output. Transitions high when a conversion is started and remains high until the conversion

is completed and the data is latched into the on-chip shift register. The falling edge of BUSY can be

used as a data-ready clock signal. Note that in master read after convert mode (MODE[1:0] = 3,

EXT/INT = low, RDC = low), the busy time changes according to Table 4.

30

TEN

DI2

Input Range Select. Used in conjunction with BIPOLAR per the following:

Input Range

BIPOLAR

TEN

0 V to 5 V

Low

Low

0 V to 10 V

Low

High

±5 V

High

Low

±10 V

High

High

31

RD

DI

Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.

32

CS

DI

Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is

also used to gate the external clock in slave serial mode (not used for serial configurable port).

33

RESET

DI

Reset Input. When high, reset the AD7634. Current conversion, if any, is aborted. The falling edge of

RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register. See

the Digital Interface section. If not used, this pin can be tied to OGND.

34

PD

DI2

Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and

conversions are inhibited after the current one is completed. The digital interface remains active

during power down.

35

CNVST

DI

Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and

initiates a conversion.