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LC863540B Fiches technique(PDF) 8 Page - Sanyo Semicon Device

No de pièce LC863540B
Description  8-bit 1-chip Microcontroller
Download  17 Pages
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Fabricant  SANYO [Sanyo Semicon Device]
Site Internet  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LC863540B Fiches technique(HTML) 8 Page - Sanyo Semicon Device

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LC863548B/40B/32B/28B/24B/20B/16B
No.7936-8/17
Pin Description
Pin name
I/O
Function
Option
VSS
-
Negative power supply
XT1
I
Input terminal for crystal oscillator
XT2
O
Output terminal for crystal oscillator
VDD
-
Positive power supply
RES
I
Reset terminal
FILT
O
Filter terminal for PLL
VS
I
Vertical synchronization signal input terminal
HS
I
Horizontal synchronization signal input terminal
R
O
Red (R) output terminal of RGB image output
G
O
Green (G) output terminal of RGB image output
B
O
Blue (B) output terminal of RGB image output
BL
O
Fast blanking control signal
Switch TV image signal and caption/OSD image signal
Port 0
P00 to P07
I/O
• 8-bit input/output port
Input/output can be specified in nibble unit
(If the N-ch open drain output is selected by option, the corresponding port data can be
read in output mode.)
• Other functions
AD converter input port (P04 to P07 : 4 channels)
Pull-up resistor
provided/not provided
Output Format
CMOS/Nch-OD
Port 1
• 8-bit input/output port
Input/output can be specified for each bit
(programmable pull-up resister provided)
• Other functions
P10
P11
P12
P13
P14
P15
P16
P17
IIC0 data I/O
IIC0 clock output
IIC1 data I/O
IIC1 clock output
PWM1 output
PWM2 output
PWM3 output
Timer 1 (PWM) output
P10 to P17
I/O
Output Format
CMOS/Nch-OD
Port 3
P30 to P33
I/O
• 4-bit input/output port
Input/output can be specified for each bit
(CMOS output/input with programmable pull-up resister)
Port 7
• 4-bit input/output port
Input or output can be specified for each bit
P70 : I/O with programmable pull-up resister
P71 to P73 : CMOS output/input with programmable pull-up resister
• Other function
P70
P71
P72
P73
INT0 input/HOLD release input/
Nch-Tr. Output for watchdog timer
INT1 input/HOLD release input
INT2 input/Timer 0 event input
INT3 input (noise rejection filter connected) /
Timer 0 event input
Interrupt receiver format, vector addresses
rising
falling
rising/
falling
H level
L level
vector
INT0
enable
enable
disable
enable
enable
03H
INT1
enable
enable
disable
enable
enable
0BH
INT2
enable
enable
enable
disable
disable
13H
P70
P71 to P73
I/O
INT3
enable
enable
enable
disable
disable
1BH
Note : A capacitor of at least 10
µF must be inserted between VDD and VSS when using this IC.
Continued on next page.


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