AD7191

Rev. A | Page 6 of 20

TIMING CHARACTERISTICS

Table 2.

Parameter1, 2

Unit

Conditions/Comments

100

ns min

SCLK high pulse width

100

ns min

SCLK low pulse width

Read Operation

0

ns min

PDOWN falling edge to DOUT/RDY active time

60

ns max

80

ns max

t23

0

ns min

SCLK active edge to data valid delay4

60

ns max

80

ns max

t55, 6

10

ns min

Bus relinquish time after PDOWN inactive edge

80

ns max

0

ns min

SCLK inactive edge to PDOWN inactive edge

10

ns min

SCLK inactive edge to DOUT/RDY high

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the

true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

6

RDY returns high after a read of the ADC. The digital word can be read only once.

1.6V

TO

OUTPUT

PIN

50pF

Figure 2. Load Circuit for Timing Characterization

TIMING DIAGRAM

PDOWN (I)

NOTES

1. I = INPUT, O = OUTPUT

DOUT/RDY (O)

SCLK (I)

Figure 3. Read Cycle Timing Diagram