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FAN6204A Fiches technique(PDF) 6 Page - ON Semiconductor

No de pièce FAN6204A
Description  Synchronous Rectification Controller
Download  16 Pages
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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© 2015 Semiconductor Components Industries, LLC.
www.onsemi.com
FAN6204A
• Rev. 1.1
5
Electrical Characteristics
VDD=15 V and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VOP
Continuously Operating Voltage
VDD-
OFF
28.5
V
VDD-ON
Turn-On Threshold Voltage
4.3
4.8
5.3
V
VDD-OFF
Turn-Off Threshold Voltage
4.0
4.5
5.0
V
VDD-HYST
VDD-ON
– VDD-OFF
0.1
0.3
0.5
V
IDD-OP
Operating Current
VDD=15 V, LPC=50 kHz, MOSFET
CISS=6000 pF
7
8
mA
IDD-GREEN
Operating Current in Green Mode
VDD=15 V
1.1
1.3
mA
IDD-ST
Startup Current
VDD< VDD-ON
150
200
A
VDD-OVP
VDD Over-Voltage Protection
26.0
27.5
28.5
V
VDD-OVP-HYST Hysteresis Voltage for VDD OVP
1.8
2.1
2.4
V
tVDD-OVP
VDD OVP Debounce Time
40
70
100
s
Output Driver Section
VZ
Gate Output Clamp Voltage
10
12
14
V
VOL
Output Voltage Low
VDD=6 V, IO=50 mA
0.5
V
VOH
Output Voltage High
VDD=6 V, IO=50 mA
4
V
tR
Rising Time
VDD=12 V, CL=6 nF, OUT=2 V~9 V
30
70
120
ns
VDD=6 V, CL=6 nF, OUT=0.4 V~4 V
70
120
170
ns
tF
Falling Time
VDD=12 V, CL=6 nF, OUT=9 V~2 V
20
50
100
ns
VDD=6 V, CL=6 nF, OUT=4 V~0.4 V
20
90
130
ns
tPD_HIGH_LPC
Propagation Delay to Turn-on
Gate (LPC Trigger)
tR: 0 V~2 V, VDD=12 V
250
ns
tPD_LOW_LPC
Propagation Delay to Turn-off
Gate (LPC Trigger)(3)
tF: 100%~90%, VDD=12 V
180
ns
tMAX-PERIOD
Limitation between LPC Rising Edge to Gate Falling Edge
22.5
25.0
28.0
s
VPMOS-ON
Internal PMOS Turn-On to Pull-HIGH Gate(3)
8.3
V
VPMOS-ON-
HYS
Hysteresis Voltage On(3)
0.9
V
tINHIBIT
Gate Inhibit Time
M2 Option (Enable)
1.6
2.2
2.8
s
VGATE-PULL-
HIGH
Gate Pull-HIGH Voltage
VDD=5 V
4.5
V
LPC Section
tBNK
Blanking Time for Charging CT
400
500
600
ns
tDELAY-COMP
Sampling Continuous Time for tBNK Compensation(3)
1
s
VLPC-SOURCE LPC Lower Clamp Voltage
Source ILPC=5 µA
0.1
0.2
0.3
V
ILPC-SOURCE
LPC Source Current
VLPC=0 V
40
80
120
A
VLPC-EN
Threshold Voltage to Enabled SR
Switching
VLPC-EN=VLPC-HIGH x 0.83 at VLPC-
HIGH
x 0.83< 2 V, VO=15 V,
VO=VDD, VLPC-HIGH=1.2 V
0.85
1.00
1.15
V
VEN-CLAMP
Threshold Clamp Voltage to
Enable SR Switching
VLPC-EN=2 V at VLPC-HIGH x 0.83 >
2 V
2
V
VLPC-TH-HIGH
Threshold Voltage on LPC Rising
Edge
Decrease VLPC from 0.05
Vo+0.05, VO=15 V, VO=VDD
0.7
0.8
0.9
V
tBNK-DIS
Blanking Time at the Falling Edge
of VLPC
Prevent LPC Spike to Turn-Off
Gate
350
ns


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