Moteur de recherche de fiches techniques de composants électroniques |
|
74ALVC573BQ Fiches technique(PDF) 2 Page - NXP Semiconductors |
|
74ALVC573BQ Fiches technique(HTML) 2 Page - NXP Semiconductors |
2 / 20 page 2003 Jun 25 2 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 FEATURES • Wide supply voltage range from 1.65 to 3.6 V • Complies with JEDEC standards: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V). • 3.6 V tolerant inputs and outputs • CMOS low power consumption • Direct interface with TTL levels (2.7 to 3.6 V) • Power-down mode • Latch-up performance exceeds 250 mA • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. DESCRIPTION The 74ALVC573 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. The 74ALVC573 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74ALVC573 is functionally identical to the 74ALVC373, but the has a different pin arrangement. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C. Notes CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 1. The condition is VI = GND to VCC. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH propagation delay input Dn to output Qn VCC = 1.8 V; CL = 30 pF; RL =1kΩ 2.5 ns VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.0 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.3 ns VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.2 ns CI input capacitance 3.5 pF CPD power dissipation capacitance per buffer VCC = 3.3 V; notes and 1 outputs enabled 37 pF outputs disabled 7 pF |
Numéro de pièce similaire - 74ALVC573BQ |
|
Description similaire - 74ALVC573BQ |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |