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74ALVC573 Fiches technique(PDF) 11 Page - NXP Semiconductors |
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74ALVC573 Fiches technique(HTML) 11 Page - NXP Semiconductors |
11 / 20 page 2003 Jun 25 11 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 handbook, full pagewidth MNA814 th tsu th tsu VM VM VI GND VI GND LE input Dn input Fig.11 Data set-up and hold times for Dn input to LE input. The shaded areas indicate when the input is permitted to change for predictable output performance. VCC VM INPUT VI tr =tf 1.65 to 1.95 V 0.5 × VCC VCC ≤ 2.0 ns 2.3 to 2.7 V 0.5 × V CC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns handbook, full pagewidth VEXT VCC VI VO MNA616 D.U.T. CL RT RL RL PULSE GENERATOR Fig.12 Load circuitry for switching times. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VCC VI CL RL VEXT tPLH/tPHL tPZH/tPHZ tPZL/tPLZ 1.65 to 1.95 V VCC 30 pF 1 k Ω open GND 2 × VCC 2.3 to 2.7 V VCC 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 6 V 3.0 to 3.6 V 2.7 V 50 pF 500 Ω open GND 6 V |
Numéro de pièce similaire - 74ALVC573 |
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Description similaire - 74ALVC573 |
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