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AD7147WPACPZ-RL Fiches technique(PDF) 8 Page - Analog Devices |
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AD7147WPACPZ-RL Fiches technique(HTML) 8 Page - Analog Devices |
8 / 71 page Data Sheet AD7147 Rev. E | Page 7 of 70 I2C TIMING SPECIFICATIONS (AD7147-1) TA = −40°C to +85°C, sample tested at 25°C to ensure compliance. VDRIVE = 1.65 V to 3.6 V, and VCC = 2.6 V to 3.6 V, unless otherwise noted. All input signals timed from a voltage level of 1.6 V. Table 5. I2C Timing Specifications1 Parameter Limit Unit Description fSCLK 400 kHz max t1 0.6 μs min Start condition hold time, tHD; STA t2 1.3 μs min Clock low period, tLOW t3 0.6 μs min Clock high period, tHIGH t4 100 ns min Data setup time, tSU; DAT t5 300 ns min Data hold time, tHD; DAT t6 0.6 μs min Stop condition setup time, tSU; STO t7 0.6 μs min Start condition setup time, tSU; STA t8 1.3 μs min Bus-free time between stop and start conditions, tBUF tR 300 ns max Clock/data rise time tF 300 ns max Clock/data fall time 1 Guaranteed by design, not production tested. I2C Timing Diagram SCLK SDA tR tF t2 t5 t1 t3 t4 STOP START STOP START t7 t6 t1 t8 Figure 3. I2C Detailed Timing Diagram 200µA IOL 200µA IOH 1.6V TO OUTPUT PIN CL 50pF Figure 4. Load Circuit for Digital Output Timing Specifications |
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