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AD9235 Fiches technique(PDF) 5 Page - Analog Devices |
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AD9235 Fiches technique(HTML) 5 Page - Analog Devices |
5 / 41 page AD9235 Data Sheet Rev. D | Page 4 of 40 DIGITAL SPECIFICATIONS Table 2. Parameter Temp Test Level AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65 Unit Min Typ Max Min Typ Max Min Typ Max LOGIC INPUTS High Level Input Voltage Full IV 2.0 2.0 2.0 V Low Level Input Voltage Full IV 0.8 0.8 0.8 V High Level Input Current Full IV –10 +10 –10 +10 –10 +10 µA Low Level Input Current Full IV –10 +10 –10 +10 –10 +10 µA Input Capacitance Full V 2 2 2 pF LOGIC OUTPUTS1 DRVDD = 3.3 V High-Level Output Voltage Full IV 3.29 3.29 3.29 V (IOH = 50 µA) High-Level Output Voltage Full IV 3.25 3.25 3.25 V (IOH = 0.5 mA) Low-Level Output Voltage Full IV 0.2 0.2 0.2 V (IOL = 1.6 mA) Low-Level Output Voltage Full IV 0.05 0.05 0.05 V (IOL = 50 µA) DRVDD = 2.5 V High-Level Output Voltage Full IV 2.49 2.49 2.49 V (IOH = 50 µA) High-Level Output Voltage Full IV 2.45 2.45 2.45 V (IOH = 0.5 mA) Low-Level Output Voltage Full IV 0.2 0.2 0.2 V (IOL = 1.6 mA) Low-Level Output Voltage Full IV 0.05 0.05 0.05 V (IOL = 50 µA) 1 Output voltage levels measured with 5 pF load on each output. SWITCHING SPECIFICATIONS Table 3. Parameter Temp Test Level AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65 Unit Min Typ Max Min Typ Max Min Typ Max CLOCK INPUT PARAMETERS Maximum Conversion Rate Full VI 20 40 65 MSPS Minimum Conversion Rate Full V 1 1 1 MSPS CLK Period Full V 50.0 25.0 15.4 ns CLK Pulse-Width High1 Full V 15.0 8.8 6.2 ns CLK Pulse-Width Low1 Full V 15.0 8.8 6.2 ns DATA OUTPUT PARAMETERS Output Delay2 (tPD) Full V 3.5 3.5 3.5 ns Pipeline Delay (Latency) Full V 7 7 7 Cycles Aperture Delay (tA) Full V 1.0 1.0 1.0 ns Aperture Uncertainty Jitter (tJ) Full V 0.5 0.5 0.5 ps rms Wake-Up Time3 Full V 3.0 3.0 3.0 ms OUT-OF-RANGE RECOVERY TIME Full V 1 1 2 Cycles 1 For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models. 2 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. 3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB. |
Numéro de pièce similaire - AD9235_17 |
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Description similaire - AD9235_17 |
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