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AD9229ABCPZ-65 Fiches technique(PDF) 7 Page - Analog Devices

No de pièce AD9229ABCPZ-65
Description  Serial, LVDS, 3 V A/D Converter
Download  41 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD9229ABCPZ-65 Fiches technique(HTML) 7 Page - Analog Devices

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AD9229
Rev. B | Page 6 of 40
SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 4.
AD9229-50
AD9229-65
Parameter
Temp
Test
Level
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK
Maximum Clock Rate
Full
VI
50
65
MSPS
Minimum Clock Rate
Full
IV
10
10
MSPS
Clock Pulse Width High
(tEH)
Full
VI
8
10
6.2
7.7
ns
Clock Pulse Width Low
(tEL)
Full
VI
8
10
6.2
7.7
ns
OUTPUT PARAMETERS
Propagation Delay (tPD)
Full
VI
3.3
6.5
7.9
3.3
6.5
7.9
ns
Rise Time (tR)
(20% to 80%)
Full
V
250
250
ps
Fall Time (tF)
(20% to 80%)
Full
V
250
250
ps
FCO Propagation Delay
(tFCO)
Full
V
6.5
6.5
ns
DCO Propagation Delay
(tCPD)
Full
V
tFCO +
(tSAMPLE/24)
tFCO +
(tSAMPLE/24)
ns
DCO-to-Data Delay (tDATA)
Full
IV
(tSAMPLE/24) –
250
(tSAMPLE/24)
(tSAMPLE/24) +
250
(tSAMPLE/24) –
250
(tSAMPLE/24)
(tSAMPLE/24) +
250
ps
DCO-to-FCO Delay (tFRAME)
Full
IV
(tSAMPLE/24) –
250
(tSAMPLE/24)
(tSAMPLE/24) +
250
(tSAMPLE/24) –
250
(tSAMPLE/24)
(tSAMPLE/24) +
250
ps
Data-to-Data Skew
(tDATA-MAX – tDATA-MIN)
Full
IV
±100
±250
±100
±250
ps
Wake-Up Time
25°C
V
4
4
ms
Pipeline Latency
Full
IV
10
10
CLK
cycles
APERTURE
Aperture Delay (tA)
25°C
V
1.8
1.8
ns
Aperture Uncertainty
(Jitter)
25°C
V
<1
<1
ps
rms
OUT-OF-RANGE RECOVERY
TIME
25°C
V
2
2
CLK
cycles


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