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AD9216 Fiches technique(PDF) 4 Page - Analog Devices

No de pièce AD9216
Description  10-Bit, 65/80/105 MSPS Dual A/D Converter
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD9216 Fiches technique(HTML) 4 Page - Analog Devices

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AD9216
Rev. A | Page 3 of 40
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 1.
Temp
Test
AD9216BCPZ-65
AD9216BCPZ-80
AD9216BCPZ-105
Parameter
Level
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
Full
VI
10
10
10
Bits
ACCURACY
No Missing Codes
Full
VI
Guaranteed
Guaranteed
Guaranteed
Offset Error
Full
VI
-1.9
±0.3
+1.9
-1.9
±0.3
+1.9
−2.2
±0.3
+2.2
% FSR
Gain Error1
25°C
VI
-1.6
±0.4
+1.6
-1.6
±0.4
+1.6
−1.6
±0.4
+1.6
% FSR
Differential Nonlinearity (DNL)2
Full
IV
-1.0
±0.3
+1.0
-1.0
±0.4
+1.0
−1.0
±0.5
+1.0
LSB
25°C
I
-0.9
±0.3
+0.9
-0.9
±0.4
+0.9
−1.0
±0.5
+1.0
LSB
Integral Nonlinearity (INL)2
Full
IV
-1.4
±0.5
+1.4
-1.6
±0.5
+1.6
−2.5
±1.0
+2.5
LSB
25°C
I
-1.0
±0.5
+1.0
-1.1
±0.5
+1.1
−1.5
±1.0
+1.5
LSB
TEMPERATURE DRIFT
Offset Error
Full
V
±10
±10
±10
µV/°C
Gain Error1
Full
V
±75
±75
±75
ppm/°C
Reference Voltage
Full
V
±15
±15
±15
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error
Full
VI
±2
±35
±2
±35
±2
±35
mV
Load Regulation @ 1.0 mA
25°C
V
1.0
1.0
1.0
mV
INPUT REFERRED NOISE
Input Span = 2.0 V
25°C
V
0.5
0.5
0.5
LSB rms
ANALOG INPUT
Input Span, VREF = 1.0 V
Full
IV
2
2
2
V p-p
Input Capacitance3
25°C
V
2
2
2
pF
REFERENCE INPUT RESISTANCE
25°C
V
7
7
7
kΩ
POWER SUPPLIES
Supply Voltages
AVDD
Full
IV
2.7
3.0
3.3
2.7
3.0
3.3
2.7
3.0
3.3
V
DRVDD
Full
IV
2.25
2.5
3.3
2.25
2.5
3.3
2.25
2.5
3.3
V
Supply Current
IAVDD4
Full
VI
72
80
78
85
100
110
mA
IDRVDD4
Full
VI
15
18
24
mA
PSRR
25°C
V
±0.1
±0.1
±0.1
% FSR
POWER CONSUMPTION
PAVDD4
25°C
I
216
240
234
255
300
330
mW
PDRVDD4
25°C
V
38
45
60
mW
Standby Power5
25°C
V
3.0
3.0
3.0
mW
MATCHING CHARACTERISTICS
Offset Matching Error6
25°C
I
-2.6
±0.2
+2.6
-2.6
±0.2
+2.6
−3.5
±0.3
+3.5
% FSR
Gain Matching Error (Shared Reference
Mode)
25°C
I
-0.4
±0.1
+0.4
-0.4
±0.1
+0.4
−0.6
±0.1
+0.6
% FSR
Gain Matching Error (Nonshared
Reference Mode)
25°C
I
-1.6
±0.1
+1.6
-1.6
±0.1
+1.6
−1.6
±0.3
+1.6
% FSR
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2 Measured with low frequency ramp at maximum clock rate.
3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure
for the equivalent analog input structure.
37
4 Measured with low frequency analog input at maximum clock rate with approximately 5 pF loading on each output bit.
5 Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
6 Both shared reference mode and nonshared reference mode.


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