MPC92432

TIMING SOLUTIONS

3

MOTOROLA

Table 1. Signal Configuration

Pin

I/O

Type

Function

XTAL1, XTAL2

Input

Analog

Crystal oscillator interface

REF_CLK

Input

LVCMOS

PLL external reference input

REF_SEL

Input

LVCMOS

Selects the reference clock input

QA

Output

Differential LVPECL

High frequency clock output

QB

Output

Differential LVPECL

High frequency clock output

LOCK

Output

LVCMOS

PLL lock indicator

M[9:0]

Input

LVCMOS

PLL feedback divider configuration

NA[2:0]

Input

LVCMOS

PLL post-divider configuration for output QA

NB

Input

LVCMOS

PLL post-divider configuration for output QB

P

Input

LVCMOS

PLL pre-divider configuration

P_LOAD

Input

LVCMOS

Selects the programming interface

SDA

I/O

LVCMOS

SCL

Input

LVCMOS

ADR[1:0]

Input

LVCMOS

BYPASS

Input

LVCMOS

Selects the static circuit bypass mode

TEST_EN

Input

LVCMOS

Factory test mode enable. This input must be set to logic low level in all applications

of the device.

CLK_STOPx

Input

LVCMOS

Output Qx disable in logic low state

MR

Input

LVCMOS

Device master reset

GND

Supply

Ground

Negative power supply

Supply

Positive power supply for the PLL (analog power supply). It is recommended to use

Supply

Positive power supply for I/O and core

Freescale Semiconductor, Inc.

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