INDUSTRIALTEMPERATURERANGE

QS5917T

LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

3

Pin Names

I/O

Description

I

Reference clock input

I

Referenceclockinput

REF_SEL

I

FREQ_SEL

I

VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.

FEEDBACK

I

PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency

relationships.SeetheFrequencySelectionTableformoreinformation.

O

Clockoutputs

O

Clock output. Matched in frequency, but inverted with respect to Q.

2xQ

O

Clock output. Matched in phase, but frequency is double the Q frequency.

Q/2

O

Clock output. Matched in phase, but frequency is half the Q frequency.

LOCK

O

PLLlockindicationsignal.1indicatespositivelock.0indicatesthatthePLLisnotlockedandoutputsmaynotbesynchronizedtotheinputs.

RST

I

Asynchronousreset.Resetsalloutputregisters.When0,alloutputsareheldinatri-statedcondition.When1,outputsareenabled(normal

operation).

PLL_EN

I

PLL enable. When 1, PLL is enabled (normal operation). When 0, PLL is disabled (for testing purposes).

N C

—

No Connection

PIN DESCRIPTION

OUTPUT FREQUENCY SPECIFICATIONS

Symbol

Description

– 70

–100

–132

Units

Max Frequency, 2xQ output

70

100

132

MHz

35

50

66

MHz

Max Frequency, Q/2 output

17.5

25

33

MHz