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AD9208BBPZRL-3000 Fiches technique(PDF) 8 Page - Analog Devices |
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AD9208BBPZRL-3000 Fiches technique(HTML) 8 Page - Analog Devices |
8 / 137 page Data Sheet AD9208 Rev. 0 | Page 7 of 136 AIN = −2 dBFS AIN = −9 dBFS Parameter2 Min Typ Max Min Typ Max Unit WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC fIN = 255 MHz −89 −90 dBFS fIN = 255 MHz (2.04 V p-p Setting) −90 −90 dBFS fIN = 765 MHz −90 −89 dBFS fIN = 900 MHz −89 −90 dBFS fIN = 1800 MHz −81 −94 dBFS fIN = 2100 MHz −80 −98 dBFS fIN = 2600 MHz −75 −84 −90 dBFS fIN = 3950 MHz −80 −90 dBFS TWO-TONE, THIRD-ORDER INTERMODULATION DISTORTION (IMD3) fIN1 = 1.842 GHz, fIN2 = 1.847 GHz, AIN1 and AIN2 = −8.0 dBFS −73 dBFS fIN1 = 1.842 GHz, fIN2 = 1.847 GHz, AIN1 and AIN2 = −15.0 dBFS −87 dBFS fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −8.0 dBFS −69 dBFS fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −15.0 dBFS −88 dBFS fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −8.0 dBFS; Full-Scale Voltage (VFS) = 1.13 V p-p −75 dBFS fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −15.0 dBFS; VFS = 1.13 V p-p −111 dBFS CROSSTALK4 >90 >90 dB Overrange Condition5 >90 >90 dB ANALOG INPUT BANDWIDTH, FULL POWER6 5 5 GHz 1 The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to+ 85°C. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 3 Noise density is measured at a low analog input frequency (30 MHz). 4 Crosstalk is measured at 950 MHz with a −1.0 dBFS analog input on one channel, and no input on the adjacent channel. 5 The overrange condition is specified with 3 dB of the full-scale input range. 6 Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved. DIGITAL SPECIFICATIONS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD = 1.9 V, specified maximum sampling rate, 1.7 V p-p full-scale differential input, AIN = −2.0 dBFS, L = 8, M = 2, F = 1, −10°C ≤ TJ ≤ +120°C,1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C). Table 3. Parameter Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance LVDS/LVPECL Differential Input Voltage 300 800 1800 mV p-p Input Common-Mode Voltage 0.675 V Input Resistance (Differential) 106 Ω Input Capacitance 0.9 pF Differential Input Return Loss at 3 GHz2 −9.4 dB SYSTEM REFERENCE (SYSREF) INPUTS (SYSREF+, SYSREF−) Logic Compliance LVDS/LVPECL Differential Input Voltage 400 800 1800 mV p-p Input Common-Mode Voltage 0.675 2.0 V Input Resistance (Differential) 18 kΩ Input Capacitance (Differential) 1 pF LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY, FD_A/GPIO_A0, FD_B/GPIO_B0, GPIO_A1, GPIO_B1) Logic Compliance CMOS Logic 1 Voltage 0.65 × SPIVDD V Logic 0 Voltage 0 0.35 × SPIVDD V Input Resistance 30 kΩ |
Numéro de pièce similaire - AD9208BBPZRL-3000 |
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Description similaire - AD9208BBPZRL-3000 |
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