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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TPS7A53-Q1 Fiches technique(PDF) 10 Page - Texas Instruments |
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TPS7A53-Q1 Fiches technique(HTML) 10 Page - Texas Instruments |
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10 / 28 page  GND VBG + ± VIN VFB GND VPG EN GND UVLOBIAS UVLOIN 10 TPS7A53-Q1 SBVS298 – SEPTEMBER 2017 www.ti.com Product Folder Links: TPS7A53-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 7.3.2.2.1 Enable (EN) The enable signal (VEN) is an active-high digital control that enables the LDO when the enable voltage is past the rising threshold (VEN ≥ VIH(EN)) and disables the LDO when the enable voltage is below the falling threshold (VEN ≤ VIL(EN)). The exact enable threshold is between VIH(EN) and VIL(EN) because EN is a digital control. Connect EN to VIN if enable functionality is not desired. 7.3.2.2.2 Undervoltage Lockout (UVLO) Control The UVLO circuits respond quickly to glitches on IN or BIAS and attempts to disable the output of the device if either of these rails collapse. 7.3.2.2.3 Active Discharge When either EN or UVLO is low, the device connects a resistor of several hundred ohms from VOUT to GND, discharging the output capacitance. Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops below the targeted output voltage. Current flows from the output to the input (reverse current) when VOUT > VIN, which can cause damage to the device (when VOUT > VIN + 0.3 V). 7.3.2.3 Power-Good Output (PG) The PG signal provides an easy solution to meet demanding sequencing requirements because PG signals when the output nears its nominal value. PG can be used to signal other devices in a system when the output voltage is near, at, or above the set output voltage (VOUT(nom)). A simplified schematic is shown in Figure 4. The PG signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active high. The PG circuit sets the PG pin into a high-impedance state to indicate that the power is good. Using a large feed-forward capacitor (CFF) delays the output voltage and, because the PG circuit monitors the FB pin, the PG signal can indicate a false positive. Figure 4. Simplified PG Circuit |
Numéro de pièce similaire - TPS7A53-Q1 |
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Description similaire - TPS7A53-Q1 |
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