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TPSM846C23MOLR Fiches technique(PDF) 7 Page - Texas Instruments |
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TPSM846C23MOLR Fiches technique(HTML) 7 Page - Texas Instruments |
7 / 82 page 7 TPSM846C23 www.ti.com SLVSDF3C – MARCH 2017 – REVISED AUGUST 2017 Product Folder Links: TPSM846C23 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) Over –40°C to 105°C free-air temperature range, VIN = 12 V, VOUT = 1.2 V, IOUT = IOUT max, ƒSW = 500 kHz, CIN1 = 4 × 22-µF, 25-V, 1210 ceramic; CIN2 = 2 × 330-µF, 25-V, electrolytic bulk; COUT1 = 4 × 47-µF, 6.3-V, 1210 ceramic; COUT2 = 2 × 470-µF, 6.3-V polymer bulk (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (5) Functionality Verified. Limits guaranteed at internal IC test. (6) Specified by design. (7) The minimum required output capacitance consists of 4 × 47-µF ceramic capacitors and 2 × 470-µF, 10 mΩ ESR (5 mΩ equivalent). (8) The proper frequency compensation network values are determined by the total amount of output capacitance. (See the Setting the Compensation Network section.) (9) The maximum ESR refers to the combined equivalent ESR of all non-ceramic output capacitors. For example, two 10 mΩ ESR capacitors have a combined equivalent ESR of 5 mΩ. POWER GOOD (PGOOD) AND OVERVOLTAGE / UNDERVOLTAGE THRESHOLD(5) VPG(OL) PGOOD Output Low Voltage VIN = 4.0 V, VOUT = 0 V, IPGOOD = 5 mA 0.3 V VIN = 0 V, IPGOOD = 80 µA 0.8 VPG(rise) PGOOD threshold VOUT rising VOUT setting = 1.2 V 95 %VO VPG(fall) PGOOD threshold VOUT falling 105 %VO VOVWARN Overvoltage warning threshold 112 %VO VOVFAULT Overvoltage fault threshold 117 %VO VUVWARN Undervoltage warning threshold 88 %VO VUVFAULT Undervoltage fault threshold 83 %VO PERFORMANCE η Efficiency (6) VIN = 12 V, IOUT = 25 A VOUT = 0.8 V 83% VOUT = 1.2 V 87% VOUT = 1.8 V 90% VIN = 5 V, IOUT = 25 A VOUT = 0.8 V 84% VOUT = 1.2 V 88% VOUT = 1.8 V 91% Transient response (6) 10A / µs load step from 25% to 75% of IOUT(max), COUT = 1000 µF, RC = 1.0 kΩ, CC = 1.0 nF VOUT over/undershoot 60 mV Recovery time 60 µs 10A / µs load step from 25% to 75% of IOUT(max), COUT = 2000 µF, RC = 665 Ω, CC = 1.5 nF VOUT over/undershoot 40 mV Recovery time 60 µs 10A / µs load step from 25% to 75% of IOUT(max), COUT = 4000 µF, RC = 499 Ω, CC = 2.2 nF VOUT over/uncdershoot 27 mV Recovery time 60 µs INTERNAL LDO (BP6, BP3) (5) VBP6 BP6 regulator output voltage 7.5V ≤ VIN ≤ 15 V, switching 5.85 6.4 6.95 V VBP6 (DO) Dropout Voltage (VVIN – VBP6), VIN = 4.5V, switching 400 mV VBP3 BP3 regulator output voltage VIN ≥ 4.5 V 3 3.2 3.4 V CAPACITANCE CIN External input capacitance ceramic 88 µF non-ceramic 660 µF COUT External output capacitance ceramic(7) 188 µF non-ceramic(7) 940 4000(8) µF ESR (9) 5 mΩ |
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