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TPD2E001-Q1 Fiches technique(PDF) 3 Page - Texas Instruments |
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TPD2E001-Q1 Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 24 page IO2 GND IO1 V CC 2 3 4 1 GND V CC N.C. IO1 IO2 2 3 4 5 1 GND V CC N.C. IO1 IO2 N.C. GND 4 5 6 3 2 1 IO1 N.C. N.C. IO2 GND V CC 3 2 6 5 4 1 3 TPD2E001 www.ti.com SLLS684I – JULY 2006 – REVISED MARCH 2016 Product Folder Links: TPD2E001 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated 5 Pin Configuration and Functions DRY Package 6-Pin USON Top View N.C. – Not internally connected DRL Package 5-Pin SOT Top View N.C. – Not internally connected DRS Package 6-Pin WSON Top View N.C. – Not internally connected DZD Package 4-Pin SOP Top View Pin Functions PIN DESCRIPTION NAME DRY NO. DRL NO. DRS NO. DZD NO. EP — — EP — Exposed pad. Connect to GND. GND 4 4 4 1 Ground IOx 3, 6 3, 5 3, 6 2, 3 ESD-protected channel N.C. 2, 5 2 2, 5 — No connection. Not internally connected. VCC 1 1 1 4 Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor. |
Numéro de pièce similaire - TPD2E001-Q1 |
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Description similaire - TPD2E001-Q1 |
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