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ADC12L066 Fiches technique(PDF) 1 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
No de pièce ADC12L066
Description  12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC12L066 Fiches technique(HTML) 1 Page - National Semiconductor (TI)

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ADC12L066
12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with
Internal Sample-and-Hold
General Description
The ADC12L066 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 66 Megasamples per second (MSPS), mini-
mum, with typical operation possible up to 80 MSPS. This
converter uses a differential, pipeline architecture with digital
error correction and an on-chip sample-and-hold circuit to
minimize die size and power consumption while providing
excellent dynamic performance. A unique sample-and-hold
stage yields a full-power bandwidth of 450 MHz. Operating
on a single 3.3V power supply, this device consumes just
357 mW at 66 MSPS, including the reference current. The
Power Down feature reduces power consumption to just
50 mW.
The differential inputs provide a full scale input swing equal
to ±V
REF with the possibility of a single-ended input. Full use
of the differential input is recommended for optimum perfor-
mance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differ-
ential reference for use by the processing circuitry. Output
data format is 12-bit offset binary.
This device is available in the 32-lead LQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C. An evaluation board is available to facilitate the
evaluation process.
Features
n
Single supply operation
n
Low power consumption
n
Power down mode
n
On-chip reference buffer
Key Specifications
n
Resolution
12 Bits
n
Conversion Rate
66 MSPS
n
Full Power Bandwidth
450 MHz
n
DNL
±0.4 LSB (typ)
n
SNR (f
IN = 10 MHz)
66 dB (typ)
n
SFDR (f
IN = 10 MHz)
80 dB (typ)
n
Data Latency
6 Clock Cycles
n
Supply Voltage
+3.3V ± 300 mV
n
Power Consumption, 66 MHz
357 mW (typ)
Applications
n
Ultrasound and Imaging
n
Instrumentation
n
Cellular Base Stations/Communications Receivers
n
Sonar/Radar
n
xDSL
n
Wireless Local Loops
n
Data Acquisition Systems
n
DSP Front Ends
Connection Diagram
20032801
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
December 2003
© 2003 National Semiconductor Corporation
DS200328
www.national.com


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