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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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HT86A36 Fiches technique(PDF) 40 Page - Holtek Semiconductor Inc |
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HT86A36 Fiches technique(HTML) 40 Page - Holtek Semiconductor Inc |
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40 / 68 page  HT86Axx/HT86ARxx Rev. 1.10 40 December 12, 2012 Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown lo- cations, due to certain uncontrollable external events such as electrical noise. It operates by providing a de- vice reset when the WDT counter overflows. The WDT clock is supplied by one of two sources selected by con- figuration option: its own self-contained dedicated inter- nal WDT oscillator, or the instruction clock which is the system clock divided by 4. Note that if the WDT configu- ration option has been disabled, then any instruction re- lating to its operation will result in no operation. The internal WDT oscillator has an approximate period of 65 ms at a supply voltage of 5V. If selected, it is first di- vided by 256 via an 8-stage counter to give a nominal period of 17ms. Note that this period can vary with VDD, temperature and process variations. For longer WDT time-out periods the WDT prescaler can be utilized. By writing the required value to bits 0, 1 and 2 of the WDTS register, known as WS0, WS1 and WS2, longer time-out periods can be achieved. With WS0, WS1 and WS2 all equal to 1, the division ratio is 1:128 which gives a maxi- mum time-out period of about 2.1s. A configuration option can select the instruction clock, which is the system clock divided by 4, as the WDT clock source instead of the internal WDT oscillator. If the in- struction clock is used as the clock source, it must be noted that when the system enters the Power Down Mode, as the system clock is stopped, then the WDT clock source will also be stopped. Therefore the WDT will lose its protecting purposes. In such cases the sys- tem cannot be restarted by the WDT and can only be re- started using external signals. For systems that operate in noisy environments, using the internal WDT oscillator is therefore the recommended choice. Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO. How- ever, if the system is in the Power Down Mode, when a WDT time-out occurs, only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the WDT and the WDT prescaler. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instructions and the third is via a ²HALT² instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the sin- gle ²CLR WDT² instruction while the second is to use the two commands ²CLR WDT1² and ²CLR WDT2². For the first option, a simple execution of ²CLR WDT² will clear the WDT while for the second option, both ²CLR WDT1 ² and ²CLR WDT2² must both be executed to successfully clear the WDT. Note that for this second option, if ²CLR WDT1² is used to clear the WDT, succes- sive executions of this instruction will have no effect, only the execution of a ²CLR WDT2² instruction will clear the WDT. Similarly, after the ²CLR WDT2² instruc- tion has been executed, only a successive ²CLR WDT1² instruction can clear the Watchdog Timer. W S 2 W D T S R e g i s t e r b 7 b 0 W D T p r e s c a l e r r a t e s e l e c t W S 2 0 0 0 0 1 1 1 1 W S 1 0 0 1 1 0 0 1 1 W S 0 0 1 0 1 0 1 0 1 W D T R a t e 1 : 1 1 : 2 1 : 4 1 : 8 1 : 1 6 1 : 3 2 1 : 6 4 1 : 1 2 8 N o t u s e d W S 1 W S 0 Watchdog Timer Register |
Numéro de pièce similaire - HT86A36_12 |
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Description similaire - HT86A36_12 |
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