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RX634 Fiches technique(PDF) 78 Page - Renesas Technology Corp

No de pièce RX634
Description  54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory
Download  106 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RX634 Fiches technique(HTML) 78 Page - Renesas Technology Corp

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R01DS0255EJ0100 Rev.1.00
Page 78 of 106
Feb 25, 2015
RX634 Group
5. Electrical Characteristics
Figure 5.17
External Bus Timing/External Wait Control
Table 5.23
Bus Timing (Multiplexed Bus)
Conditions 1: VCC = AVCC0 = VREFH0 = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
Ta = –40 to +85°C
Conditions 2: VCC = AVCC0 = VREFH0 = 4.0 to 5.5 V, VREFH = 4.0 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
Ta = –40 to +85°C
fBCLK
≤ 54 MHz (BCLK pin output frequency ≤ 27 MHz), VOH = VCC × 0.5, V
OL = VCC × 0.5, IOH = –1.0 mA,
IOL = 1.0 mA, CL = 30 pF
Item
Symbol
Min.
Max.
Unit
Test Conditions
Address delay time
tAD
30
ns
Figure 5.18,
Figure 5.19
Byte control delay time
tBCD
—30
ns
CS# delay time
tCSD
—30
ns
RD# delay time
tRSD
—30
ns
ALE delay time
tALED
—30
ns
Read data setup time
tRDS
20
ns
Read data hold time
tRDH
0—
ns
WR# delay time
tWRD
—30
ns
Write data delay time
tWDD
—30
ns
Write data hold time
tWDH
0—
ns
WAIT# setup time
tWTS
20
ns
Figure 5.17
WAIT# hold time
tWTH
0—
ns
tWTS tWTH
tWTS tWTH
CSRWAIT:3
CSWWAIT:3
BCLK
A23 to A0
CS3# to CS0#
RD# (Read)
WR# (Write)
WAIT#
TW1
TW2
(Tend)Tend
TW3
Tn1
Th
External wait


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