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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TRF3750 Fiches technique(PDF) 3 Page - Texas Instruments |
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TRF3750 Fiches technique(HTML) 3 Page - Texas Instruments |
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3 / 32 page  TRF3750 SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004 www.ti.com 3 ORDERING INFORMATION PRODUCT PACKAGE / LEADS PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA QUANTITY TRF3750IPW TSSOP-16 PW –40°C to 85°C TRF3750 TRF3750IPW Tube 90 TRF3750IPWR TSSOP-16 PW –40°C to 85°C TRF3750 TRF3750IPWR Reel 2000 TRF3750IRGP QFN-20 RGP –40°C to 85°C TRF3750 TRF3750IRGP Tube 91 TRF3750IRGPR QFN-20 RGP –40°C to 85°C TRF3750 TRF3750IRGPR Reel 1000 PIN ASSIGNMENTS TERMINAL NAME QFN(1) NO. TSSOP NO. TYPE DESCRIPTION RSET 19 1 O The user needs to place an external resistor (RSET) from this pin to ground to control the maximum charge pump current. This node’s output voltage is typically around 1 V and the relationship between ICPOUTmax and RSET is: ICPOUTmax + 23.5 RSET A 4.7-kΩ resistor placed at this pin to ground would hence provide a maximum charge pump output current of approximately 5 mA. CPOUT 20 2 O Charge pump output. This node provides the charge pump current that ultimately controls the external VCO. CPGND 1 3 I Charge pump ground AGND 23 4 I Analog ground RFIN 4 5 I Complementary input to the prescaler. For single-ended applications, bypass with a small capacitor to ground (typically 100 pF). RFIN 5 6 I Input to the prescaler. To complete the PLL, this signal must come from the output of the external VCO. AVDD 6, 7 7 I Analog power supply. There are two possible supply ranges: 3 V − 3.6 V and 4.5 V − 5.5 V. This value should be the same as the DVDD. Appropriate decoupling is necessary for optimal performance. REFIN 8 8 I Reference frequency input. This externally provided reference gets divided by the selectable R divider, and is used to synthesize the desired output frequency. Typically this input is an ac-coupled sinusoid; however, a TTL or CMOS signal can also be used. DGND 9, 10 9 I Digital ground CE 11 10 I Chip enable. Setting this pin low puts the device into power down; setting it high activates the charge pump if the software controlled power down is also disabled. CLOCK 12 11 I Serial clock input. This is the input that is used to clock the serial data into the 24-bit shift register of the device. The data is read at the rising edge of this clock. DATA 13 12 I Serial data input. This is the data stream that contains the data to be loaded into the shift register. The data is loaded MSB first. LE 14 13 I Load enable. When this asynchronous signal is asserted high, the data existing in the shift register get loaded onto the selected latch. MUXOUT 15 14 O This user-selectable output can be controlled to provide the digital or analog lock detect signals, the divide by N RF signal or the divide by R reference. The output can also be 3-stated. DVDD 16, 17 15 I Digital power supply. There are two possible supply ranges: 3 V − 3.6 V and 4.5 V − 5.5 V. This value should be the same as the AVDD. Appropriate decoupling is necessary for optimal performance. VCP 18 16 I Charge pump supply. This supply must be at least 1 V greater than the AVDD and DVDD and can be as high as 8 V, accommodating a large range of possible VCOs. (1) The thermal pad on the bottom of the QFN package may be tied to ground, but is not required to meet specified performance. |
Numéro de pièce similaire - TRF3750 |
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Description similaire - TRF3750 |
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