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CS5529-AP Fiches technique(PDF) 8 Page - Cirrus Logic |
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CS5529-AP Fiches technique(HTML) 8 Page - Cirrus Logic |
8 / 30 page CS5529 8 DS246F1 SWITCHING CHARACTERISTICS (T A = 25 °C; VA ± = ±2.5 V ±5%, VD+ = 3 V ±5% or 5 V ±5%; Input Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50pF) Notes: 19. Device parameters are specified with 32.768 kHz clock, however, clocks up to 100 kHz can be used for increased throughput. 20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. Parameter Symbol Min Typ Max Unit Master Clock Frequency: External Clock or Internal Oscillator (Note19) XIN 30 32.768 100 kHz Master Clock Duty Cycle 40 - 60 % Rise Times (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output trise - - - - - 50 1.0 100 - µs µs ns Fall Times (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output trise - - - - - 50 1.0 100 - µs µs ns Start-up Oscillator Start-up Time XTAL = 32.768 kHz (Note 21) tost -500 - ms Power-on Reset Period tpor - 1002 - XIN cycles Serial Port Timing Serial Clock Frequency SCLK 0 - 2 MHz Serial Clock Pulse Width High Pulse Width Low t1 t2 250 250 - - - - ns ns SDI Write Timing CS Enable to Valid Latch Clock t3 50 - - ns Data Set-up Time prior to SCLK rising t4 50 - - ns Data Hold Time After SCLK Rising t5 100 - - ns SCLK Falling Prior to CS Disable t6 100 - - ns SDO Read Timing CS to Data Valid t7 -- 150 ns SCLK Falling to New Data Bit t8 -- 150 ns CS Rising to SDO Hi-Z t9 -- 150 ns |
Numéro de pièce similaire - CS5529-AP |
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Description similaire - CS5529-AP |
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