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SZNUP4114 Fiches technique(PDF) 6 Page - ON Semiconductor |
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SZNUP4114 Fiches technique(HTML) 6 Page - ON Semiconductor |
6 / 9 page NUP4114 Series, SZNUP4114 Series http://onsemi.com 6 Implementing this topology with discrete devices does have disadvantages. This configuration is shown below: VCC D1 D2 Data Line IESDpos IESDneg VF + VCC −VF IESDpos IESDneg Power Supply Protected Device Looking at the figure above, it can be seen that when a positive ESD condition occurs, diode D1 will be forward biased while diode D2 will be forward biased when a negative ESD condition occurs. For slower transient conditions, this system may be approximated as follows: For positive pulse conditions: Vc = VCC + VfD1 For negative pulse conditions: Vc = −VfD2 ESD events can have rise times on the order of some number of nanoseconds. Under these conditions, the effect of parasitic inductance must be considered. A pictorial representation of this is shown below. VCC D1 D2 Data Line IESDpos IESDneg VC = VCC + Vf + (L diESD/dt) IESDpos IESDneg Power Supply Protected Device VC = −Vf − (L diESD/dt) An approximation of the clamping voltage for these fast transients would be: For positive pulse conditions: Vc = VCC + Vf + (L diESD/dt) For negative pulse conditions: Vc = −Vf – (L diESD/dt) As shown in the formulas, the clamping voltage (Vc) not only depends on the Vf of the steering diodes but also on the L diESD/dt factor. A relatively small trace inductance can result in hundreds of volts appearing on the supply rail. This endangers both the power supply and anything attached to that rail. This highlights the importance of good board layout. Taking care to minimize the effects of parasitic inductance will provide significant benefits in transient immunity. Even with good board layout, some disadvantages are still present when discrete diodes are used to suppress ESD events across datalines and the supply rail. Discrete diodes with good transient power capability will have larger die and therefore higher capacitance. This capacitance becomes problematic as transmission frequencies increase. Reducing capacitance generally requires reducing die size. These small die will have higher forward voltage characteristics at typical ESD transient current levels. This voltage combined with the smaller die can result in device failure. The ON Semiconductor NUP4114 was developed to overcome the disadvantages encountered when using discrete diodes for ESD protection. This device integrates a TVS diode within a network of steering diodes. Figure 7. NUP4114 Equivalent Circuit 5 3 6 2 1 4 During an ESD condition, the ESD current will be driven to ground through the TVS diode as shown below. VCC D1 D2 Data Line IESDpos Power Supply Protected Device The resulting clamping voltage on the protected IC will be: Vc = VF + VTVS. The clamping voltage of the TVS diode depends on the magnitude of the ESD current. The steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics. |
Numéro de pièce similaire - SZNUP4114 |
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Description similaire - SZNUP4114 |
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