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9ZXL1950 Datasheet(Fiches technique) 1 Page - Integrated Device Technology

Numéro de pièce 9ZXL1950
Description  19-Output DB1900Z Low-Power Derivative with 85ohm Terminations
Télécharger  18 Pages
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Fabricant  IDT [Integrated Device Technology]
Site Internet  http://www.idt.com
Logo IDT - Integrated Device Technology

9ZXL1950 Datasheet(HTML) 1 Page - Integrated Device Technology

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DATASHEET
9ZXL1950 MAY 11, 2017
1
©2017 Integrated Device Technology, Inc.
19-Output DB1900Z Low-Power Derivative
with 85ohm Terminations
9ZXL1950
General Description
The 9ZXL1950 is a DB1900Z derivative buffer utilizing
Low-Power HCSL (LP-HCSL) outputs to increase edge rates
on long traces, reduce board space, and reduce power
consumption more than 50% from the original 9ZX21901.It is
pin-compatible to the 9ZXL1930 and fully integrates the
output terminations. It is suitable for PCI-Express Gen1/2/3 or
QPI/UPI applications, and uses a fixed external feedback to
maintain low drift for demanding QPI/UPI applications.
Recommended Application
Buffer for Romley, Grantley and Purley Servers
Output Features
19 LP-HCSL output pairs w/integrated terminations (Zo =
85

Key Specifications
Cycle-to-cycle jitter: <50ps
Output-to-output skew: <50ps
Input-to-output delay variation: <50ps
Phase jitter: PCIe Gen3 <1ps rms
Phase jitter: QPI/UPI 9.6GB/s <0.2ps rms
Features/Benefits
LP-HCSL outputs; up to 90% IO power reduction, better
signal integrity over long traces
Direct connect to 85Ω transmission lines; eliminates 76
termination resistors, saves 130mm2 area
Pin compatible to the 9ZXL1930; easy upgrade to reduced
board space
72-pin VFQFPN package; smallest 19-output Z-buffer
Fixed feedback path; ~0ps input-to-output delay
9 Selectable SMBus addresses; multiple devices can share
same SMBus segment
Separate VDDIO for outputs; allows maximum power
savings
PLL or bypass mode; PLL can dejitter incoming clock
100MHz & 133.33MHz PLL mode; legacy QPI support
Selectable PLL BW; minimizes jitter peaking in downstream
PLL's
Spread spectrum compatible; tracks spreading input clock
for EMI reduction
SMBus Interface; unused outputs can be disabled
Block Diagram
Logic
DIF(18:0)
HIBW_BYPM_LOBW#
SMBDAT
SMBCLK
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
100M_133M#
Z-PLL
(SS Compatible)
FBOUT_NC
DIF_IN
DIF_IN#


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