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USBN9603 Fiches technique(PDF) 34 Page - National Semiconductor (TI) |
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USBN9603 Fiches technique(HTML) 34 Page - National Semiconductor (TI) |
34 / 60 page 7.0 Register Set (Continued) 34 www.national.com EOP End of Packet. A valid EOP sequence was detected on the USB. It is used when this device has initiated a Remote wake-up sequence to indicate that the Resume sequence has been acknowledged and completed by the host. This bit is cleared when the register is read. SD3 Suspend Detect 3 mS. This bit is set after 3 mS of IDLE is detected on the upstream port, indicating that the device should be suspended. The suspend occurs under firmware control by writing the suspend value to the Node Functional State (NF- SR) register. This bit is cleared when the register is read. SD5 Suspend Detect 5 mS. This bit is set after 5 mS of IDLE is detected on the upstream port, indicating that this device is per- mitted to perform a remote wake-up operation. The resume may be initiated under firmware control by writing the resume value to the NFSR register. This bit is cleared when the register is read. RESET This bit is set when 2.5 µS of SEO is detected on the upstream port. In response, the functional state should be reset (NFS in the NFSR register is set to RESET), where it must remain for at least 100 µS. The functional state can then return to Op- erational state. This bit is cleared when the register is read. RESUME Resume signalling is detected on USB when the device is in Suspend state (NFS in the NFSR register is set to SUSPEND), and a non IDLE signal is present on USB, indicating that this device should begin its wake-up sequence and enter Opera- tional state. This bit is cleared when the register is read. 7.1.8 Alternate Mask Register (ALTMSK) A bit set to 1 in this register enables automatic setting of the ALT bit in the MAEV register when the respective event in the ALTEV register occurs. Otherwise, setting ALT bit is disabled. 7.1.9 Transmit Event Register (TXEV) TXFIFO Transmit FIFO. These bits are a copy of the TX_DONE bits from the corresponding Transmit Status (TXSx) registers. The bits are set when the IN transaction for the corresponding transmit endpoint is complete. The bits are cleared when the cor- responding TXSx register is read. TXUDRRN Transmit Underrun. These bits are copies of the respective TX_URUN bits from the corresponding TXSx registers. When- ever any of the Transmit FIFOs underflow, the respective TXUDRRN bit is set. These bits are cleared when the correspond- ing Transmit Status register is read. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Same Bit Definition as ALTEV Register 0 0 0 0 000 - r/w - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TXFIFO3 TXFIFO2 TXFIFO1 FIFO0 TXFIFO3 TXFIFO2 TXFIFO1 FIFO0 TXUDRRN3-0 TXFIFO3-0 0000 0 0 0 0 r 1 1. Since Endpoint 0 implements a store and forward principle, an underrun condition for FIFO0 cannot occur. This results in the TXUDRRN0 bit always being read as 0. r |
Numéro de pièce similaire - USBN9603 |
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Description similaire - USBN9603 |
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