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TPS54418 Fiches technique(PDF) 4 Page - Texas Instruments

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No de pièce TPS54418
Description  2.95-V to 6-V Input, 4-A Output, 2-MHz , Synchronous Step-Down Switcher With Integrated FETs (SWIFT)
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS54418 Fiches technique(HTML) 4 Page - Texas Instruments

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TPS54418
SLVS946D – SEPTEMBER 2009 – REVISED DECEMBER 2014
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
EN, PWRGD, VIN
–0.3
7
RT/CLK
–0.3
6
Input voltage
V
COMP, SS, VSENSE
–0.3
3
BOOT
VPH+ 8 V
BOOT-PH
8
Output voltage
PH
–0.6
7
V
PH (10 ns transient)
–2
7
Source current
EN, RT/CLK
100
µA
COMP, SS
100
µA
Sink current
PWRGD
10
mA
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V
V(ESD)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification JESD22-C101, all
±500
V
pins(2)
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VVIN
Input voltage
3
6
V
TJ
Operating junction temperature
–40
150
°C
7.4 Thermal Information
(1)
TPS54418
THERMAL METRIC(2)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
50
RθJA
Junction-to-ambient thermal resistance (3)
37
RθJC(top)
Junction-to-case (top) thermal resistance
59.1
RθJB
Junction-to-board thermal resistance
23.1
°C/W
ψJT
Junction-to-top characterization parameter
1.4
ψJB
Junction-to-board characterization parameter
23.1
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.9
(1)
Unless otherwise specified, metrics listed in this table refer to JEDEC high-K board measurements
(2)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(3)
Test Board Conditions:
(a) 2 inches × 2 inches, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground planes located on the two internal layers and bottom layer
(d) 4 thermal vias (10 mil) located under the device package
4
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Product Folder Links: TPS54418


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