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TPS7B6750QPWPRQ1 Fiches technique(PDF) 6 Page - Texas Instruments |
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TPS7B6750QPWPRQ1 Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 26 page TPS7B6701-Q1 TPS7B6733-Q1, TPS7B6750-Q1 SLVSCB2C – OCTOBER 2013 – REVISED DECEMBER 2014 www.ti.com 8.5 Electrical Characteristics VI = 14 V, 1 mΩ < ESR < 20 Ω, TJ = –40°C to 150°C unless otherwise stated PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE AND CURRENT (VIN) VI Input voltage Fixed 3.3-V output, IO = 0 to 450 mA 4 40 Fixed 5-V output, IO = 0 to 450 mA 5.5 40 V Adjustable output, VO ≤ 3.5 V, IO = 0 to 450 mA 4 40 Adjustable output, VO ≥ 3.5 V, IO = 0 to 450 mA VO + 0.5 40 VI = 5.5 to 40 V (fixed 5 V), 4 to 40 V (fixed 3.3 V), 15 25 EN = ON, IO = 0.2 mA VI = 4 to 40 V (adjustable version, VO = 1.5 V), IQ Quiescent current 15 25 µA EN = ON, IO = 0.2 mA VI = 18.5 to 40 V (Adjustable version, VO = 18 V), 25 35 EN = ON, IO = 0.2 mA ISleep Input sleep current NO load current and EN = OFF 4 µA IEN EN pin current EN = 40 V 1 µA Vbg Band gap Reference voltage for ADJ –2% 1.233 2% V VINUVLO Undervoltage detection Ramp VI down until output is turned OFF 2.6 V UVLOHys Undervoltage detection 1 V hysteresis ENABLE INPUT (EN) VIL Logic input low level 0 0.4 V VIH Logic input high level 1.7 V REGULATED OUTPUT (VOUT) VO Regulated output(1) VI = VO + 0.5 to 40 V and VI ≥ 4 V, IO = 0 to 450 mA –2% 2% ΔVO(ΔVI) Line regulation VI = VO + 1 to 40 V and VI ≥ 4 V, IO = 100 mA, ∆VO 10 mV ΔVO(ΔIL) Load regulation IO = 1 to 450 mA, ∆VO 10 mV VI – VO, IO = 400 mA 240 450 Vdropout Dropout voltage mV VI – VO, IO = 200 mA 160 300 IO Output current VO in regulation 0 450 mA VO short to ground 140 360 Ilreg-CL Output current-limit mA VO = VO typical × 0.9 470 850 Freq = 100 Hz 60 PSRR Power-supply ripple rejection(2) IL = 100 mA, CO = 22 µF dB Freq = 100 kHz 40 RESET VOL Reset pulled low IOL = 0.5 mA 0.4 V IOH Reset pulled VOUT through Leakage current 1 µA 10-k resistor VTH-(POR) Power-On-Reset threshold VO power-up set tolerance 89.6 91.6 93.6 % of VOUT Vhys Hysteresis VO power-down set tolerance 2 % of VOUT RESET DELAY IChg Delay capacitor charging Rdelay = 0 V 6 9.5 14 µA current Vth Threshold to release RESET 1 V high OPERATING TEMPERATURE RANGE TJ Junction temperature –40 150 °C Tsd Junction shutdown 175 °C temperature Thys Hysteresis of thermal 24 °C shutdown (1) External resistor divider variation is not considered. (2) Design information — Not tested, ensured by characterization 6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 |
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