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TPS7B6750-Q1 Fiches technique(PDF) 5 Page - Texas Instruments |
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TPS7B6750-Q1 Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 26 page TPS7B6701-Q1 TPS7B6733-Q1, TPS7B6750-Q1 www.ti.com SLVSCB2C – OCTOBER 2013 – REVISED DECEMBER 2014 8 Specifications 8.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Unregulated input range(2)(3)(4) VIN, EN –0.3 45 V VOUT –0.3 22 V Output range DELAY(2)(3)(5) 45 V ADJ, RESET 22 V Operating junction temperature (TJ) –40 150 °C Storage temperature (Tstg) –65 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability (2) All voltage values are with respect to GND. (3) Absolute negative voltage on these pins does not go below –0.3 V. (4) Absolute maximum voltage. (5) The voltage at the DELAY pin must be lower than the VIN voltage. 8.2 ESD Ratings VALUE UNIT Human-body model (HBM), per AEC Q100-002(1)(2) ±2000 All pins ±500 V(ESD) Electrostatic discharge V Charged-device model (CDM), per AEC Corner pins (1, 10, 11, Q100-011 ±750 and 20) (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. (2) The human body model is a 107-pF capacitor discharged through a 1.5-k Ω resistor into each pin. 8.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Unregulated input range VIN 4 40 V EN, DELAY 0 40 V Output range VOUT, RESET, ADJ 1.5 18 V TJ Operating junction temperature range –40 150 °C 8.4 Thermal Information PWP (HTSSOP) THERMAL METRIC(1)(2) UNIT 20 PINS θJA Junction-to-ambient thermal resistance 44.9 θJCtop Junction-to-case (top) thermal resistance 27.4 θJB Junction-to-board thermal resistance 23.6 °C/W ψJT Junction-to-top characterization parameter 1.1 ψJB Junction-to-board characterization parameter 23.4 θJCbot Junction-to-case (bottom) thermal resistance 3.1 (1) The thermal data is based on JEDEC standard high K profile — JESD 51-7. Two signal, two plane, four-layer board with 2-oz copper. The copper pad is soldered to the thermal land pattern. Also correct attachment procedure must be incorporated. (2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 |
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