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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TPS7A6301QPWPRQ1 Fiches technique(PDF) 11 Page - Texas Instruments |
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TPS7A6301QPWPRQ1 Fiches technique(HTML) 11 Page - Texas Instruments |
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11 / 41 page  VIN(POWERUP) VIN VOUT 0 0 V = 93% of V TH(POR) OUT VTH(RDELAY) VRDELAY VnRST tPOR 0 0 VIN VOUT 0 0 VTH(POR) VnRST 0 0 t < tDEGLITCH UVTHRES tDEGLITCH t>tDEGLITCH tPOR VTH(RDELAY) VRDELAY POR 6 CDLY 3 t 1 10- ´ = ´ TPS7A6301-Q1, TPS7A6333-Q1, TPS7A6350-Q1, TPS7A6401-Q1 www.ti.com SLVSAB1E – JUNE 2011 – REVISED SEPTEMBER 2015 7.3 Feature Description 7.3.1 Power Up, Reset Delay, and Reset Output During power up, the regulator incorporates a protection scheme to limit the current through the pass element and output capacitor. When the input voltage exceeds a certain threshold (VIN(POWERUP)) level, the output voltage begins to ramp up as shown in Figure 16. When starting up, and also when the output recovers from a negative voltage spike due to a load step or a dip in the input voltage for a specified duration, the device implements reset delay to indicate that output voltage is stable and in regulation. When the output voltage reaches the power-on-reset threshold (VTH(POR)) level, that is, 93% of regulated output voltage (3.3 V or 5 V, or a programmed value), a constant output current charges an external capacitor (CDLY) to an internal threshold (VTH(RDELAY)) voltage level. Then, nRST asserts high and CDLY discharges through an internal load. This allows CDLY to charge from approximately 0 V during the next power cycle. Program the reset delay time by connecting an external capacitor (CDLY ,100 pF to 100 nF) to the RDELAY pin. Equation 1 gives the delay time: where • tPOR = reset delay time in seconds • CDLY = reset delay capacitor value in farads (1) Figure 16. Power Up and Conditions for Activation Figure 17. Reset Delay and Deglitch Filter of Reset As Figure 17 shows, if the regulated output voltage falls below 93% of the set level, nRST asserts low after a short de-glitch time of approximately 5.5 µs (typical). In case of negative transients in the input voltage (VIN), the reset signal asserts low only if the output (VOUT) drops and stays below the reset threshold level (VTH(POR)) for more than the deglitch time (tDEGLITCH), as Figure 17 and Figure 20 illustrate. While nRST is low, if the input voltage returns to the nominal operating voltage, the normal power-up sequence ensues. nRST asserts high only if the output voltage exceeds the reset threshold voltage (VTH(POR)) and the reset delay time (tPOR) has elapsed. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1 |
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