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TPS7A1601-Q1 Fiches technique(PDF) 10 Page - Texas Instruments |
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TPS7A1601-Q1 Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 29 page 10 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 SBVS188D – MARCH 2012 – REVISED MAY 2016 www.ti.com Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated 7.4 Device Functional Modes 7.4.1 Power-Good The power-good (PG) pin is an open-drain output and can be connected to any 5.5-V or lower rail through an external pullup resistor. When no CDELAY is used, the PG output is high-impedance when VOUT is greater than the PG trip threshold (VIT). If VOUT drops below VIT, the open-drain output turns on and pulls the PG output low. If output voltage monitoring is not needed, the PG pin can be left floating or connected to GND. To ensure proper operation of the power-good feature, maintain VIN ≥ 3 V (VIN_MIN). 7.4.1.1 Power-Good Delay and Delay Capacitor The power-good delay time (tDELAY) is defined as the time period from when VOUT exceeds the PG trip threshold voltage (VIT) to when the PG output is high. This power-good delay time is set by an external capacitor (CDELAY) connected from the DELAY pin to GND; this capacitor is charged from 0 V to ap 1.8 V by the DELAY pin current (IDELAY) once VOUT exceeds the PG trip threshold (VIT). When CDELAY is used, the PG output is high-impedance when VOUT exceeds VIT, and VDELAY exceeds VREF. The power-good delay time can be calculated using: tDELAY = (CDELAY × VREF)/IDELAY. For example, when CDELAY = 10 nF, the PG delay time is approximately 12 ms; that is, (10 nF × 1.193 V)/1 µA = 11.93 ms. |
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