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TPS92210 Fiches technique(PDF) 7 Page - Texas Instruments |
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TPS92210 Fiches technique(HTML) 7 Page - Texas Instruments |
7 / 30 page FB 1 2 3 4 TZE PCL OTM VDD GND DRN VCG 8 7 6 5 TPS92210 www.ti.com SLUS989B – JANUARY 2010 – REVISED SEPTEMBER 2012 PIN CONFIGURATION PIN DESCRIPTIONS TERMINAL I/O DESCRIPTION NAME No. The DRN pin is the drain of the internal low voltage power MOSFET of the TPS92210 and carries the peak primary DRN 6 O inductor current, IPEAK(pri). Connect this pin to the source of the external cascode power MOSFET. A schottky diode between DRN and VDD is used to provide initial bias at startup. The FB pin is regulated at 0.7 V and only detects current input (FB current,IFB) which commands the operating mode of TPS92210. For peak-current mode control, this pin is connected to the emitter of the feedback opto FB 1 I coupler. In constant on-time control, the minimum switching period is programmed by forcing a constant current into this pin. This GND pin is the current return terminal for both the analog and power signals in the TPS92210. This terminal GND 7 — carries the full drain current, IDRN, which is equal to the peak primary current, IPEAK(pri), in addition to the bias supply current (IVDD) , and the gate voltage current (IVCG). the OTM pin is internally regulated at 3 V and used to program the on-time of the cascode (flyback) switch by connecting a resistor (ROTM) from this pin to the quiet return of GND. The collector of the opto-coupler is connected OTM 4 I to this pin for constant-on time control. The range of impedance connected at this pin determines the system fault response (latch-off or shutdown/retry) to overload and brownout fault conditions. An external shutdown/retry response can be initiated by pulling this pin low below 1 V. The PCL pin programs the peak primary inductor current that is reached each switching cycle. The primary current PCL 3 I is sensed with the RDS(on) of the internal MOSFET and is programmed by setting a threshold by connecting a low power resistor from this pin to the quiet return of GND. A resistive divider between the primary-side auxiliary winding and this pin is used to detect when the transformer is TZE 2 I demagnetized resulting in transformer zero energy. The ratio of the resistive divider at this pin can also be used to program the output overvoltage protection (OVP) feature. The VCG pin provides the bias voltage for the gate of the cascode MOSFET. Place a 0.1-µF ceramic capacitor VCG 5 — between VCG and GND, as close as possible to the high-voltage MOSFET. This pin also provides start-up bias through a resistor RSU, which is connected between this pin and the bulk voltage. VDD is the bias supply pin for the TPS92210. It can be derived from an external source, or an auxiliary winding. VDD 8 — Place a 0.1-µF ceramic capacitor between VDD and GND, as close to the device as possible. This pin also enables and disables the general functions of the TPS92210 using the UVLO feature. Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS92210 |
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