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TPS70202PWPRG4 Fiches technique(PDF) 9 Page - Texas Instruments |
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TPS70202PWPRG4 Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 37 page VIN1 VUVLO VUVLO t t t MR Input RESET Output 120ms Delay 120ms Delay NOTEA: V .ThesymbolV RES RES RESET istheminimuminputvoltageforavalid isnotcurrentlylistedwithinEIAorJEDECstandardsfor semiconductorsymbology. VRES (seeNoteA) Output Undefined Output Undefined VRES (seeNoteA) VPG t t t PG1 Output VIT+ (seeNoteB) VIN1 VOUT1 VPG1 (seeNoteA) V (seeNoteB) VUVLO VUVLO PG1 NOTES: A. V istheminimuminputvoltageforavalidPG1.ThesymbolV isnotcurrentlylistedwithinEIAorJEDEC PG1 PG1 standards forsemiconductorsymbology. B. V tripvoltageistypically5%lowerthantheoutputvoltage(95%V ). toV i O IT+ sthehysteresisvoltage. IT- V IT- Threshold Voltage Output Undefined Output Undefined IT- TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E – JUNE 2000 – REVISED DECEMBER 2009 RESET Timing Diagram PG1 Timing Diagram Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 9 |
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