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TPS3808G30DRVR Fiches technique(PDF) 7 Page - Texas Instruments |
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TPS3808G30DRVR Fiches technique(HTML) 7 Page - Texas Instruments |
7 / 32 page Time 0.8V 0.0V V IT + VHYS V IT 0.7V DD 0.3V DD MR SENSE RESET V DD t D t D t D t D = Reset Delay = Undefined State 7 TPS3808 www.ti.com SBVS050K – MAY 2004 – REVISED OCTOBER 2015 Product Folder Links: TPS3808 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated (1) RLRESET and CLRESET are the resistor and capacitor connected to the RESET pin. 7.6 Switching Characteristics 1.7 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to 125°C), unless otherwise noted. Typical values are at TJ = 25°C. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tw Input pulse width to RESET SENSE VIH = 1.05 VIT, VIL = 0.95 VIT 20 μs MR VIH = 0.7 VDD, VIL = 0.3 VDD 0.001 td RESET delay time CT = Open See Figure 1 12 20 28 ms CT = VDD 180 300 420 CT = 100 pF 0.75 1.25 1.75 CT = 180 nF 0.7 1.2 1.7 s Propagation delay MR to RESET VIH = 0.7 VDD, VIL = 0.3 VDD 150 ns High-to-low level RESET delay SENSE to RESET VIH = 1.05 VIT, VIL = 0.95 VIT 20 μs Figure 1. TPS3808 Timing Diagram Showing MR and SENSE Reset Timing |
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Description similaire - TPS3808G30DRVR |
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