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TP3404 Fiches technique(PDF) 3 Page - National Semiconductor (TI) |
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TP3404 Fiches technique(HTML) 3 Page - National Semiconductor (TI) |
3 / 14 page Electrical Characteristics Unless otherwise specified limits printed in BOLD characters are guaranteed for VCCA e VCCD e 5V g5% TA e 0 Cto a70 C Typical characteristics are specified at VDDA e VDDD e 50V TA e 25 C All signals are referenced to GND which is the common of GNDA and GNDD (Continued) TIMING SPECIFICATIONS (Continued) Symbol Parameter Conditions Min Typ Max Units DIGITAL INTERFACE TIMING fBCLK BCLK Frequency 4096 41 MHz tWBH Clock Pulse Width High Measured from VIH to VIH 70 ns tWBL and Low for BCLK Measured from VIL to VIL 70 tRB Rise Time and Fall Time Measured from VIL to VIH 15 ns tFB of BCLK Measured from VIH to VIL 15 tHBM BCLK Transition to MCLK High or Low b 30 30 ns tSFC Set up Time FS Valid to BCLK Invalid 20 4ns tHCF Hold Time BCLK Low to FS Invalid 40 30 ns tSBC Setup Time BI Valid to BCLK Invalid 30 11 ns tHCB Hold Time BCLK Valid to BI Invalid 40 7ns tSDC Setup Time DI Valid to BCLK Low 30 ns tHCD Hold Time BCLK Low to DI Invalid 40 ns tDCB Delay Time BCLK High to BO Valid Load e 2 LSTTL a 100 pF 80 ns tDCBZ Delay Time BCLK Low to BO High-Z 80 120 ns tDCD Delay Time BCLK High to DO valid Load e 2 LSTTL a 100 pF 80 ns tDCZ Delay Time BCLK Low to DO High 40 120 ns Impedance tDCT Delay Time BCLK High to TSB Low 120 ns tZBT Disable Time BCLK Low to TSB High-Z 120 ns MICROWIRE CONTROL INTERFACE TIMING fCCLK Frequency of CCLK 21 MHz tCH Period of CCLK High Measured from VIH to VIH 150 ns tCL Period of CCLK Low Measured from VIL to VIL 150 ns tSSC Setup Time CS Low to CCLK High 50 ns tHCS Hold Time CCLK High to CS Transition 40 ns tSIC Setup Time CI Valid to CCLK High 50 ns tHCI Hold Time CCLK High to CI Invalid 20 ns tDCO Delay Time CCLK Low to CO Valid 80 ns tDSOZ Delay Time CS High to CO High-Z 80 ns tDCIZ Delay Time CCLK to INT High-Z 100 ns Notes For the purposes of this specification the following conditions apply a All input signals are defined as VIL e 04V VIH e 27V tr k 10 ns tf k 10 ns b Delay times are measured from the input signal Valid to the output signal Valid c Setup times are measured from the Data input Valid to the clock input Invalid d Hold times are measured from the clock signal Valid to the Data input Invalid 3 |
Numéro de pièce similaire - TP3404 |
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Description similaire - TP3404 |
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