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TS1103 Fiches technique(PDF) 8 Page - Silicon Laboratories |
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TS1103 Fiches technique(HTML) 8 Page - Silicon Laboratories |
8 / 12 page TS1103 Page 8 TS1103 Rev. 1.1 external VSENSE, op amp feedback action drives the gate of M1 such that M1’s drain-source current is equal to: I DS(M1)= VSENSE RGAINA or IDS(M1)= ILOADx RSENSE RGAINA Since M1’s drain terminal is connected to ROUT, the output voltage of the TS1103 at the OUT terminal is, therefore; VOUT=ILOADx RSENSEx ROUT RGAINA When the voltage at the RS- terminal is greater than the voltage at the RS+ terminal, the external VSENSE voltage drop is impressed upon RGAINB. The voltage drop across RGAINB is then converted into a current by M2 that then produces an output voltage across ROUT. In this design, when M1 is conducting current (VRS+ > VRS-), the TS1103’s internal amplifier holds M2 OFF. When M2 is conducting current (VRS- > VRS+), the internal amplifier holds M1 OFF. In either case, the disabled FET does not contribute to the resultant output voltage. The current-sense amplifier’s gain accuracy is therefore the ratio match of ROUT to RGAIN[A/B]. For each of the four gain options available, Table 1 lists the values for ROUT and RGAIN[A/B]. The TS1103’s output stage is protected against input overdrive by use of an output current-limiting circuit of 3mA (typical) and a 7V internal clamp protection circuit. Table 1: Internal Gain Setting Resistors (Typical Values) GAIN (V/V) RGAIN[A/B] ( Ω) ROUT ( Ω) Part Number 25 400 10k TS1103-25 50 200 10k TS1103-50 100 100 10k TS1103-100 200 100 20k TS1103-200 The SIGN Comparator Output As shown in the TS1103’s block diagram, the design of the TS1103 incorporated one additional feature – an analog comparator the inputs of which monitor the internal amplifier’s differential output voltage. While the voltage at the TS1103’s OUT terminal indicates the magnitude of the load current, the TS1103’s SIGN output indicates the load current’s direction. The SIGN output is a logic high when M1 is conducting current (VRS+ > VRS-). Alternatively, the SIGN output is a logic low when M2 is conducting current (VRS+ < VRS-). The SIGN comparator’s transfer characteristic is illustrated in Figure 1. Unlike other current-sense amplifiers that implement a OUT/SIGN arrangement, the TS1103 exhibits no “dead zone” at ILOAD switchover. Figure 1: TS1103's SIGN Comparator Transfer Characteristic. Figure 2: SIGN Comparator Propagation Delay vs VSENSE. 100 0.1 10 1 VSENSE (│VRS+ - VRS-│) - mV 0.1 1 10 100 |
Numéro de pièce similaire - TS1103 |
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Description similaire - TS1103 |
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