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TC94A14F Fiches technique(PDF) 10 Page - Toshiba Semiconductor

No de pièce TC94A14F
Description  Digital Servo Single-Chip Processor for Use in CD Player
Download  17 Pages
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Fabricant  TOSHIBA [Toshiba Semiconductor]
Site Internet  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC94A14F Fiches technique(HTML) 10 Page - Toshiba Semiconductor

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TC94A14F/FA/FB
2002-11-18
10
3.
DATA, CLCK Input/Output Timing
(1)
CLCK input mode (regardless of setting of HS and UHS bits of SPEED command)
Characteristics
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
“H” level
tHW
¾
50
¾
¾
Clock pulse width
“L” level
tLW
¾
CLCK input mode
50
¾
¾
Input setup time
tSU
¾
CLCK input mode
¾
¾
¾
Transfer time (1)
“L” level
tpHL1
¾
CLCK input mode
¾
¾
5
“H” level
tpLH52
¾
¾
¾
15
“L” level
tpHL52
¾
CLCK input mode
¾
¾
15
“H” level
tpLH52
¾
¾
¾
20
Transfer time (2)
“L” level
tpHL52
¾
VDD5 = 3.3 V
¾
¾
20
ns
(2)
CLCK output mode (tHW, tLW, tpLH3 only, ´ 1/n at ´n speed)
Characteristics
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
“H” level
tHW
¾
¾
¾
950
Clock pulse width
“L” level
tLW
¾
CLCK output mode
¾
¾
950
Transfer time (1)
“L” level
tpHL1
¾
CLCK output mode
¾
¾
5
“H” level
tpLH52
¾
¾
¾
15
“L” level
tpHL52
¾
CLCK output mode
¾
¾
15
“H” level
tpLH32
¾
¾
¾
20
Transfer time (2)
“L” level
tpHL32
¾
VDD5 = 3.3 V
¾
¾
20
Transfer time (3)
“H” level
tpLH3
¾
CLCK output mode
¾
¾
850
ns
SUBQ
SUBP
SFSY
CLCK
DATA
tpHL1
tpHL52, tpLH52
tHW
tSU
tLW
tpHL32, tpLH32
SUBQ
SUBP
SFSY
CLCK
DATA
tpHL1
tpHL52, tpLH52
tHW
tpLH3
tLW
tpHL32, tpLH32


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