CDCV857B, CDCV857BI

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010

5

POST OFFICE BOX 655303

recommended operating conditions (see Note 4)

MIN

TYP

MAX

UNIT

Supply voltage

2.3

2.7

V

Supply voltage

2.7

V

Low level input voltage V

CLK, CLK, FBIN, FBIN

V

PWRDWN

−0.3

0.7

V

High level input voltage V

CLK, CLK, FBIN, FBIN

V

PWRDWN

1.7

V

DC input signal voltage (see Note 5)

–0.3

V

Differential input signal voltage V (see Note 6)

dc

CLK, FBIN

0.36

V

ac

CLK, FBIN

0.7

V

V

−12

mA

12

mA

Input slew rate, SR

1

4

V/ns

Operating free air temperature T

Commercial

0

85

°C

Industrial

−40

85

°C

NOTES: 4. The unused inputs must be held high or low to prevent them from floating.

5. The dc input signal voltage specifies the allowable dc execution of the differential input.

6. The differential input signal voltage specifies the differential voltage |VTR − VCP| required for switching, where VTR is the true input

level and VCP is the complementary input level.

be crossing.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

Input voltage

All inputs

–1.2

V

V

High level output voltage

V

High-level output voltage

1.7

V

V

Low level output voltage

0.1

V

Low-level output voltage

0.6

V

Differential outputs are terminated

with 120 Ω /CL 14 pF (See

1.1

V

with 120 Ω /CL = 14 pF (See

Figure 3)

V

Input current

±10

μA

High-impedance state output current

±10

μA

Power-down current on

CLK and CLK = 0 MHz; PWRDWN

20

100

μA

AI

Supply current on AV

7

10

mA

9

12

mA

Input capacitance

2

2.5

3.5

pF

complementary output level.

The frequency range is 100 MHz to 200 MHz.