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KM29W040AT Fiches technique(PDF) 11 Page - Samsung semiconductor |
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KM29W040AT Fiches technique(HTML) 11 Page - Samsung semiconductor |
11 / 22 page KM29W040AT, KM29W040AIT FLASH MEMORY 11 System Interface Using CE don’t-care. CE WE tWP tCH tCS Start Add.(3Cycle) 80H Data Input CE CLE ALE WE I/O0~7 Data Input CE don’t-care 10H For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 32byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption. Start Add.(3Cycle) 00H CE CLE ALE WE I/O0~7 Data Output(sequential) CE don’t-care R/B tR RE tCEA out tREA (Max. 60ns) CE RE I/O0~7 Timing requirements : If CE is is exerted high during sequential data-reading, the falling edge of CE to valid data(tCEA) must be kept greater than 60ns. Figure 3. Program Operation with CE don’t-care. Figure 4. Read Operation with CE don’t-care. |
Numéro de pièce similaire - KM29W040AT |
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Description similaire - KM29W040AT |
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