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ADC10D020EVAL Fiches technique(PDF) 11 Page - National Semiconductor (TI) |
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ADC10D020EVAL Fiches technique(HTML) 11 Page - National Semiconductor (TI) |
11 / 32 page AC Electrical Characteristics OS = High (Parallel Mode) (Continued) 20025506 Note 8: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Note 9: Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Performance is guaranteed only at VREF = 1.0V and a clock duty cycle of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are performed and limits guaranteed with clock low and high levels of 0.3V and VD − 0.3V, respectively. Note 10: IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR =VDR (CO xfO +C1 xf1 +...+C9 xf9) where VDR is the output driver power supply voltage, Cn is the total capacitance on the output pin, and fn is the average frequency at which that pin is toggling. Timing Diagrams 20025508 ADC10D020 Timing Diagram for Multiplexed Mode www.national.com 11 |
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