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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TSC2100IRHBR Fiches technique(PDF) 11 Page - Texas Instruments |
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TSC2100IRHBR Fiches technique(HTML) 11 Page - Texas Instruments |
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11 / 71 page  TSC2100 SLAS378− NOVEMBER 2003 www.ti.com 11 LRCK/ADWS BCLK DOUT DIN tL(BCLK) ts (DI) th (DI) tS (WS) tH(BCLK) td(DO−BCLK) th(WS) tP(BCLK) th(WS) tS (WS) Figure 4. DSP Timing in Slave Mode TYPICAL TIMING REQUIREMENTS (FIGURE 4) All specifications at 25 °C, DVDD = 1.8 V (1) PARAMETER IOVDD = 1.1 V IOVDD = 3.3 V UNITS PARAMETER MIN MAX MIN MAX UNITS tH (BCLK) BCLK high period 35 35 ns tL (BCLK) BCLK low period 35 35 ns ts(WS) ADWS/LRCK setup 6 6 ns th(WS) ADWS/LRCK hold 6 6 ns td (DO−BCLK) BCLK to DOUT delay 25 15 ns ts(DI) DIN setup 6 6 ns th(DI) DIN hold 6 6 ns tr Rise time 5 4 ns tf Fall time 5 4 ns (1) These parameters are based on characterization and are not tested in production. |
Numéro de pièce similaire - TSC2100IRHBR |
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Description similaire - TSC2100IRHBR |
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