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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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SX48BD Fiches technique(PDF) 14 Page - List of Unclassifed Manufacturers |
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SX48BD Fiches technique(HTML) 14 Page - List of Unclassifed Manufacturers |
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14 / 58 page  © 2002 Ubicom, Inc. All rights reserved. - 14 - www.ubicom.com SX48BD/SX52BD 4.0 SPECIAL-FUNCTION REGISTERS The CPU uses a set of special-function registers to con- trol operation of the device. The CPU registers include an 8-bit working register (W), which serves as a pseudo accumulator. It holds the sec- ond operand of an instruction, receives the literal in immediate type instructions, and also can be program- selected as the destination register. A set of 31 file registers serves as the primary accumula- tor. One of these registers holds the first operand of an instruction and another can be program-selected as the destination register. The first 10 file registers include the Real-Time Clock/Counter register (RTCC), the lower eight bits of the 12-bit Program Counter (PC), the 8-bit STATUS register, five port control registers for Ports A through E, the 8-bit File Select Register (FSR), and INDF (used for indirect addressing). The five low-order bits of the FSR register select one of the 31 file registers in the indirect addressing mode. Call- ing for the file register located at address 00h (INDF) in any of the file-oriented instructions selects indirect addressing, which uses the FSR register. It should be noted that the file register at address 00h is not a physi- cally implemented register. The CPU also contains an 8- level, 12-bit hardware push/pop stack for subroutine link- age. 4.1 PC Register (02h) The PC register holds the lower eight bits of the program counter. It is accessible at run time to perform branch operations. The upper three bits are located in the STA- TUS register (PA2:0), bit 8 is not accessible. 4.2 STATUS Register (03h) The STATUS register holds the arithmetic status of the ALU, the page select bits, and the reset state. The STA- TUS register is accessible during run time, except that bits PD and TO are read-only. It is recommended that only SETB and CLRB instructions be used on this regis- ter. Care should be exercised when writing to the STA- TUS register as the ALU status bits are updated upon completion of the write operation, possibly leaving the STATUS register with a result that is different than intended. Table 4-1. Special-Function Registers Addr Name Function 00h INDF Used for indirect addressing 01h RTCC Real Time Clock/Counter 02h PC Program Counter (low byte) 03h STATUS Holds Status bits of ALU 04h FSR File Select Register 05h RA Port RA data register 06h RB Port RB data register 07h RC Port RC data register 08h RD Port RD data register 09h RE Port RE data register PA2 PA1 PA0 TO PD Z DC C Bit 7 Bit 0 Bit 7-5: Program memory page select bits PA2:PA0 000 = Page 0 (000h – 1FFh) 001 = Page 1 (200h – 3FFh) ... 111 = Page 7 (E00h – FFFh) Bit 4: Time Out bit, TO (Read Only) 1 = Set to 1 after power up and upon exe- cution of CLRWDT or SLEEP instructions 0 = A watchdog time-out occurred Bit 3: Power Down bit, PD (Read Only) 1= Set to a 1 after power up and upon ex- ecution of the CLR !WDT instruction 0 = Cleared to a ‘0’ upon execution of SLEEP instruction Bit 2: Zero bit, Z (affected by most logical, arithmetic, and data movement instructions 1 = Result of math operation is zero 0 = Result of math operation is non-zero Bit 1: Digit Carry bit, DC After Addition: 1 = A carry from bit 3 occurred 0 = No carry from bit 3 occurred After Subtraction: 1 = No borrow from bit 3 occurred 0 = A borrow from bit 3 occurred Bit 0: Carry bit, C After Addition: 1 = A carry from bit 7 of the result occurred 0 = No carry from bit 7 of the result oc- cured. After Subtraction: 1 = No borrow from bit 7 of the result oc- curred 0 = A borrow from bit 7 of the result oc- curred Rotate (RR or RL) Instructions: The carry bit is loaded with the low or high order bit, respectively When CF bit of the FUSEX register is cleared to 0, Carry bit works as input for ADD and SUB instructions. |
Numéro de pièce similaire - SX48BD |
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Description similaire - SX48BD |
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