HMC8100LP6JE

Data Sheet

Rev. A | Page 20 of 27

REGISTER DESCRIPTIONS

REGISTER ARRAY ASSIGNMENTS

In the Access columns (Table 6 through Table 14), R means read, W means write, and R/W means read/write.

Enable Bits

Table 6. Enable Register, (Address 0x01)

Bit No.

Bit Name

Description

Reset

Access

15

PD2_EN

Power Detector 2 enable

0x1

R/W

0 = disable

1 = enable

14

Factory diagnostics

Logic 0 for normal operation

0x0

R/W

13

PD3_AMP1_EN

Auxiliary output (Pin 13) enable

0x1

R/W

0 = disable

1 = enable

12

Reserved

Logic 1 for normal operation

0x1

R/W

11

AMP1_EN

LNA enable

0x1

R/W

0 = disable

1 = enable

10

RF_VGA_EN

RF VGA enable

0x1

R/W

0 = disable

1 = enable

9

IRM_EN

Image reject mixer enable

0x1

R/W

0 = disable

1 = enable

8

FIL2_EN

Filter 2 enable

0x1

R/W

0 = disable

1 = enable

7

IF_VGA_EN

Filter 2 enable

0x1

R/W

0 = disable

1 = enable

6

Factory diagnostics

Logic 0 for normal operation

0x0

R/W

5

PD1_EN

Power Detector 1 enable

0x1

0 = disable

1 = enable

4

PD3_EN

Power Detector 3 enable

0x1

R/W

0 = disable

1 = enable

3

AGC_EN

Available gain control (AGC) enable

0x1

R/W

0 = enable

1 = disable

2

AMP3_PDWN

Amplifier 3 power-down

0x1

R/W

0 = enable

1 = disable

1

AMP2_PDWN

0x1

R/W

Amplifier 2 power-down

0 = enable

1 = disable

0

IQ_BUF_EN

IQ buffer enable

0x0

R/W

0 = disable

1 = enable