SN74CB3Q3345

8BIT FET BUS SWITCH

2.5V/3.3V LOW VOLTAGE HIGHBANDWIDTH BUS SWITCH

SCDS144A − OCTOBER 2003 − REVISED NOVEMBER 2003

3

POST OFFICE BOX 655303

simplified schematic, each FET switch (SW)

A

EN†

B

† EN is the internal enable signal applied to the switch.

Charge

Pump

VCC

−0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±64 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

68

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 5): DGV package

92

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 5): PW package

83

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 6): RGY package

37

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. All voltages are with respect to ground unless otherwise specified.

2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. VI and VO are used to denote specific conditions for VI/O.

4. II and IO are used to denote specific conditions for II/O.

5. The package thermal impedance is calculated in accordance with JESD 51-7.

6. The package thermal impedance is calculated in accordance with JESD 51-5.

recommended operating conditions (see Note 7)

MIN

MAX

UNIT

VCC

Supply voltage

2.3

3.6

V

VIH

High-level control input voltage

VCC = 2.3 V to 2.7 V

1.7

5.5

V

VIH

High-level control input voltage

VCC = 2.7 V to 3.6 V

2

5.5

V

VIL

Low-level control input voltage

VCC = 2.3 V to 2.7 V

0

0.7

V

VIL

Low-level control input voltage

VCC = 2.7 V to 3.6 V

0

0.8

V

VI/O

Data input/output voltage

0

5.5

V

TA

Operating free-air temperature

−40

85

°C

NOTE 7: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.