 |
Moteur de recherche de fiches techniques de composants électroniques |
|
|
Moteur de recherche de fiches techniques de composants électroniques |
|
TAS5015 Fiches technique(PDF) 4 Page - Texas Instruments |
|
||||||||||||||||||||||||||||||
TAS5015 Fiches technique(HTML) 4 Page - Texas Instruments |
|
|
4 / 19 page  TAS5015 SLES017 – SEPTEMBER 2001 4 www.ti.com Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AVDD1 48 I Analog supply AVDD2 2 I Analog supply AVSS1 44, 47 I Analog ground AVSS2 5 I Analog ground DBSPD 39 I Indicates sample rate is double speed (88.2 kHz or 96 kHz), active high DEM_EN 43 I De-emphasis enable, active high DEM_SEL 42 I De-emphasis select (0 = 44.1 kHz, 1 = 48 kHz) DVDD1 12, 14 I Digital voltage supply for logic DVDD2 31 I Digital voltage supply for PWM reclocking DVDD3_L 36 I Digital voltage supply for PWM output (left) DVDD3_R 25 I Digital voltage supply for PWM output (right) DVSS1 13, 15 I Digital ground for logic DVSS2 30 I Digital ground for PWM reclocking DVSS3_L 37 I Digital ground for PWM output (left) DVSS3_R 24 I Digital ground for PWM output (right) FTEST 41 I Tied to DVSS1 for normal operation HFCLK 6 I External PLL clock input LRCLK 18 I/O Left/right clock (input when M_S = 0; output when M_S = 1) MCLK_IN 1 I MCLK input MCLK_OUT 16 O Buffered system clock output if M_S = 1; otherwise set to 0 MOD0 22 I Serial interface selection pin, bit 0 MOD1 21 I Serial interface selection pin, bit 1 MOD2 20 I Serial interface selection pin, bit 2 (MSB) M_S 10 I Master/slave, master=1, slave=0 MUTE 38 I Muted signal = 0, normal mode = 1 NC 3, 4, 11, 45, 46 No connection PDN 8 I Power down, active low PWM_AM_L 34 O PWM left output A (differential –) PWM_AM_R 28 O PWM right output A (differential –) PWM_AP_L 35 O PWM left output A (differential +) PWM_AP_R 29 O PWM right output A (differential +) PWM_BM_L 33 O PWM left output B (differential –) PWM_BM_R 27 O PWM right output B (differential –) PWM_BP_L 32 O PWM left output B (differential +) PWM_BP_R 26 O PWM right output B (differential +) RESET 7 I Reset (active low) SCLK 17 I/O Shift clock (input when M_S = 0, output when M_S = 1) SDIN 19 I Stereo serial audio data input STEST 40 I Tied to DVSS1 for normal operation VALID_L 23 O PWM left outputs valid (active high) VALID_R 9 O PWM right outputs valid (active high) |
Numéro de pièce similaire - TAS5015 |
|
Description similaire - TAS5015 |
|
|
|
Lien URL |
| Politique de confidentialité |
| ALLDATASHEET.FR |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
French ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
