74LVC16373APVG8 datasheet(5/6 Pages) IDT

No de pièce	74LVC16373APVG8

Description	3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH

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Fabricant	IDT [Integrated Device Technology]

Site Internet	http://www.idt.com

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INDUSTRIALTEMPERATURERANGE

IDT74LVC16373A

3.3VCMOS16-BIT TRANSPARENT D-TYPE LATCH

5

Open

VLOAD

GND

VCC

Pulse

Generator

D.U.T.

500



500



CL

RT

VIN

VOUT

(1, 2)

LVC Link

INPUT

VIH

0V

VOH

VOL

tPLH1

tSK (x)

OUTPUT 1

OUTPUT 2

tPHL1

tSK (x)

tPLH2

tPHL2

VT

VOH

VT

VOL

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

SAME PHASE

INPUT TRANSITION

OPPOSITE PHASE

INPUT TRANSITION

0V

VOH

VOL

tPLH

tPHL

tPLH

OUTPUT

VIH

VT

VIH

VT

LVC Link

DATA

INPUT

0V

tREM

TIMING

INPUT

ASYNCHRONOUS

CONTROL

SYNCHRONOUS

CONTROL

tSU

tH

tSU

tH

VIH

VT

VIH

VT

VIH

VT

VIH

VT

LVC Link

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

VT

tW

VT

LVC Link

CONTROL

INPUT

tPLZ

0V

OUTPUT

NORMALLY

LOW

tPZH

0V

SWITCH

CLOSED

OUTPUT

NORMALLY

HIGH

ENABLE

DISABLE

SWITCH

OPEN

tPHZ

0V

VOL+VLZ

VOH

VT

tPZL

VLOAD/2

VIH

VT

VOL

VOH-VHZ

LVC Link

TEST CIRCUITS AND WAVEFORMS

Propagation Delay

Test Circuit for All Outputs

Enable and Disable Times

Set-up, Hold, and Release Times

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

NOTES:

1. Pulse Generator for All Pulses: Rate

≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate

≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

Output Skew - tSK(X)

Pulse Width

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V

VCC(2)=2.5V±0.2V

Unit

VLOAD

6

2 x Vcc

V

VIH

2.7

Vcc

V

VT

1.5

Vcc / 2

V

VLZ

300

150

mV

VHZ

300

150

mV

CL

50

30

pF

TEST CONDITIONS

SWITCH POSITION

Test

Switch

Open Drain

Disable Low

VLOAD

Enable Low

Disable High

GND

Enable High

All Other Tests

Open

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