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SL28PCIe16ALIT Fiches technique(PDF) 8 Page - Silicon Laboratories

No de pièce SL28PCIe16ALIT
Description  Low power push-pull type differential output buffers
Download  13 Pages
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Fabricant  SILABS [Silicon Laboratories]
Site Internet  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SL28PCIe16ALIT Fiches technique(HTML) 8 Page - Silicon Laboratories

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SL28PCIe16
DOC#: SP-AP-0790 (Rev. 0.3)
Page 8 of 12
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
Crystal
LACC
Long-term Accuracy
Measured at VDD/2 differential
250
ppm
Clock Input
TDC
CLKIN Duty Cycle
Measured at VDD/2
47
53
%
TR/TF
CLKIN Rise and Fall Times
Measured between 0.2VDD and 0.8VDD
0.5
4.0
V/ns
TCCJ
CLKIN Cycle to Cycle Jitter
Measured at VDD/2
250
ps
TLTJ
CLKIN Long Term Jitter
Measured at VDD/2
350
ps
VIH
Input High Voltage
XIN / CLKIN pin
2
VDD+0.3
V
VIL
Input Low Voltage
XIN / CLKIN pin
0.8
V
IIH
Input High Current
XIN / CLKIN pin, VIN = VDD
35
uA
IIL
Input Low Current
XIN / CLKIN pin, 0 < VIN <0.8
–35
uA
SRC at 0.7V
TDC
SRC Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
100 MHz SRC Period
Measured at 0V differential at 0.1s
9.99900
10.0010
ns
TPERIODSS
100 MHz SRC Period, SSC
Measured at 0V differential at 0.1s
10.02406
10.02607
ns
TPERIODAbs
100 MHz SRC Absolute Period
Measured at 0V differential at 1 clock
9.87400
10.1260
ns
TPERIODSSAbs 100 MHz SRC Absolute Period, SSC
Measured at 0V differential at 1 clock
9.87406
10.1762
ns
TCCJ
SRC Cycle to Cycle Jitter
Measured at 0V differential
50
ps
RMSGEN1
Output PCIe* Gen1 REFCLK phase
jitter
BER = 1E-12 (including PLL BW 8 - 16
MHz, ζ = 0.54, Td=10 ns,
Ftrk=1.5 MHz)
0108
ps
RMSGEN2
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
03.0
ps
RMSGEN2
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
03.1
ps
RMSGEN3
Output phase jitter impact – PCIe*
Gen3
Includes PLL BW 2 - 4 MHz,
CDR = 10MHz)
01.0
ps
LACC
SRC Long Term Accuracy
Measured at 0V differential
100
ppm
TR / TF
SRC Rising/Falling Slew Rate
Measured differentially from ±150 mV
2.5
8
V/ns
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
1.8
ms
TSS
Stopclock Set-up Time
10.0
ns


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